G02B6/4239

THREE-DIMENTIONAL PACKAGING METHOD AND PACKAGE STRUCTURE OF PHOTONIC-ELECTRONIC CHIP
20220365295 · 2022-11-17 ·

The present disclosure provides a three-dimensional packaging method and a three-dimensional package structure of a photonic-electronic chip. The method includes: fixing an electronic chip on a first area of a first surface of a photonic chip; fixing a dummy chip on a second area of the first surface of the photonic chip, wherein the photonic chip is provided with an optical coupling interface at the second area, and the dummy chip has a cavity with a single-sided opening, and the opening of the cavity faces and covers an optical coupling interface.

PACKAGE STRUCTURE

A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

Optical Device

An optical element that is optically coupled to light inlet/outlet ends of an optical fiber is disposed on a base placed near the light inlet/outlet ends of the optical fiber. Moreover, a rod-like reinforcing member has an integral structure fixed into a first hole formed in the optical fiber and a second hole formed in the base 102.

TECHNOLOGIES FOR OPTICAL COUPLING TO PHOTONIC INTEGRATED CIRCUITS

Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In the illustrative embodiment, a lens assembly with one or more lenses is positioned to collimate light coming out of one or more waveguides in the PIC die. Part of the illustrative lens assembly extends above a top surface of the PIC die and is in contact with the PIC die. The top surface of the PIC die establishes the vertical positioning of the lens assembly. In the illustrative embodiment, the lens assembly is positioned at least partially inside a cavity defined within the PIC die, which allows the lens assembly to be integrated at the wafer level, before singulation into individual dies.

DIE FIRST FAN-OUT ARCHITECTURE FOR ELECTRIC AND OPTICAL INTEGRATION

An electronic device and associated methods are disclosed. In one example, the electronic device includes a photonic integrated circuit and an in situ formed waveguide. In selected examples, the electronic device includes a photonic integrated circuit coupled to an electronic integrated circuit, in a glass layer, where a waveguide is formed in the glass layer.

PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURES

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURES

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active side and an opposing backside, and wherein the PIC is embedded in the insulating material with the active side facing down; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the backside of the PIC and the conductive pillar; and an optical component optically coupled to the active surface of the PIC.

PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURES

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active surface and an opposing backside, and wherein the PIC is embedded in the insulating material with the active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer and the second layer includes the insulating material, wherein the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; and an optical component optically coupled to the active surface of the PIC and extending through the insulating material in the second layer.

Fiber coupler with an optical window

A fiber array unit (FAU) includes a substrate, a plurality of optical fibers, and a lid. The substrate includes: an optical window extending through a layer of non-transparent material, a plurality of grooves, and an alignment protrusion configured to mate with an alignment receiver. The plurality of optical fibers are disposed in the plurality of grooves. The alignment protrusion is configured to align the plurality of optical fibers with an external device when mated with the alignment receiver. The plurality of optical fibers is disposed between the lid and the substrate.

Fiber-to-chip coupler

A fiber-to-chip coupler includes a substrate, a waveguide on a top surface of the substrate, an optical fiber axially aligned to the waveguide, and a cap. The waveguide has a uniform region with uniform width and a tapered-waveguide region having a width that adiabatically increases from a minimum width to the uniform width. The optical fiber has a tapered fiber tip having a minimum core diameter, a cylindrical section having a maximum core diameter, and a tapered-fiber section therebetween. The optical fiber is located at least in part above the tapered-waveguide region, and has a core diameter that adiabatically decreases within a taper length of the tapered-fiber section. The cap extends from the tapered fiber tip toward the cylindrical section, is formed of a second material having a cap refractive index that exceeds a refractive index of the optical fiber, and includes a cap-region disposed on the tapered-waveguide region.