A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

In a display device having high reliability, even if being a narrow framing type, and a method for manufacturing thereof, having a display panel, being made up with a first substrate 101 and a second substrate 201, which are adhered with using a seal 301, a main SOC 302 is disposed like a wall, on a peripheral end portion of the first substrate 101 and the second substrate 201, and the seal 301 is disposed inwardly of the main SOC 302. Also, in a method for manufacturing thereof, the main SOC 302 is formed in a region including a cutting plane between the display panel regions neighboring with, and on the cutting plane is made the cutting thereof.

The present disclosure provides a liquid crystal display panel and a display device. The liquid crystal display panel includes an array substrate. A hollow structure is defined in a common electrode layer. The hollow structure includes a first hollow structure corresponding to a display area. An area of the first hollow structure progressively increases along a direction from an array routing area to the display area, so that an area of the common electrode layer corresponding to the display area progressively decreases along the direction from the array routing area to the display area, thereby making RC loadings uniform and keeping charging rates in various areas same.

Provided are a display panel and a display device. The display panel includes a display area and a non-display area surrounding the display area, the display area includes a first rectangular area and a first special-shaped area disposed adjacent to the first rectangular area, and the non-display area includes a second rectangular area adjacent to the first rectangular area and a second special-shaped area adjacent to the first special-shaped area. The display area includes pixel units arranged in an array, and a plurality of shift registers are disposed in the second rectangular area and the second special-shaped area, where each of the plurality of shift registers is connected to a row of pixel units. The second special-shaped area includes a laser cutting affected area, where none of the plurality of shift registers is disposed in at least part of the laser cutting affected area.

Embodiments of the present invention disclose an array substrate and a display panel. The array substrate includes a first substrate, and a first metal layer, a second metal layer, and a first shielding line sequentially disposed on the first substrate. The first metal layer includes a plurality of scan lines, the second metal layer includes a signal transmission line electrically connected to all of the scan lines, and at least a part of an orthographic projection of a wiring part of the signal transmission line on the first substrate coincides with an orthographic projection of the first shielding line on the first substrate.

In a liquid crystal device serving as an electro-optical device, a liquid crystal layer as an electro-optical element is disposed between a base material 10s as a first substrate and a base material 20s as a second substrate which are disposed to face each other via a photo-curable type seal material, the substrate 10s and the substrate 20s are transmissive and include a plurality of light-shielding patterns disposed at intervals in a seal region of the substrate 10s where the seal material is disposed, and on the substrate 10s, a semiconductor layer of a transistor included in a driving circuit for driving the electro-optical element is disposed to overlap, in plan view, with at least one of the plurality of light-shielding patterns.

A display substrate includes a base substrate and a plurality of insulating layers disposed on a surface of the base substrate. A groove is defined in the insulating layers in a non-display area of the display substrate. An end portion of an alignment layer is disposed in the groove. The groove is capable of controlling a flow of a liquid alignment material to prevent the liquid alignment material from overflowing to an edge of the base substrate. The groove is formed simultaneously in a process of forming contact holes in a display area of the display substrate. Accordingly, a structure corresponding to the end portion of the alignment layer to control the flow of the liquid alignment material is formed without increasing the number of masks.

A display panel having an active area includes: an array substrate and an opposite substrate disposed opposite to the array substrate. The array substrate includes a first substrate and a conductive structure disposed on the first substrate. The conductive structure is located on a side of the active area. On a side of the conductive structure away from the active area, a side surface of the conductive structure is substantially flush with a side surface of the first substrate. On the side where the conductive structure is located, an edge of an orthographic projection of the opposite substrate on a plane where the array substrate is located is located outside an edge of the array substrate.

Disclosed are a drive circuit, an array substrate and a display panel. The first signal line is for receiving and transmitting the first reset control signal after the display of the current frame ends. First ends of the first thin film transistor and the second thin film transistor are connected to the first signal line. Second ends of the first thin film transistor and the second thin film transistor are connected to the second signal line. Third ends of the first thin film transistor and the second thin film transistor are connected to the controlled end and output end of the output module, respectively. The first thin film transistor and the second thin film transistor are for outputting the DC signal to the controlled end and the output end of the output module, respectively, upon receiving the first reset control signal, to reset the output module.