Disclosed are an array substrate of a thin-film transistor liquid crystal display device and a method for manufacturing the same. The array substrate includes a plurality of data lines, a plurality of dummy data lines, a plurality of first gate lines, a plurality of second gate lines, and a plurality of groups of pixel units. Each group of pixel units includes an odd-numbered column of first thin film transistors and an even-numbered column of second thin film transistors. First ends and second ends of the dummy data lines are connected respectively to two common voltage electrode lines, which are arranged on the substrate in a transverse direction. The method includes steps of: forming a plurality of gate lines and two common voltage electrode lines; forming a source, a drain, and a plurality of data lines; and forming a plurality of pixel electrodes and a plurality of dummy data lines. A light shielding electrode line provided has good voltage driving uniformity.

The present disclosure provides a method for manufacturing an array substrate and a display device. The method for manufacturing the array substrate includes providing a substrate; disposing a metal layer material on the substrate; disposing thermal reactive photoresist material on the metal layer material; obtaining a thermal reactive photoresist layer using a mask process and a thermal reaction process; and obtaining a metal layer by an etching process.

The present invention provides a method for manufacturing a thin film transistor including processing of irradiating an amorphous silicon film 8 deposited on a substrate with laser light. The method comprises: a laser annealing step for forming a polysilicon film 9 including a channel region 52 by irradiating an area including a formation region of the region 52 in the film 8 with the laser light such that the area including the formation region is heated, melted, and recrystallized; and a removing step for etching off an area outside the region 52 from the polysilicon film 9. Thus, the present invention can provide a method for manufacturing a thin film transistor and a mask for use in the manufacturing method that are capable of promoting the recrystallization of the film 8 and thereby improving its electron mobility even when laser irradiation has to be performed under restricted irradiation conditions.

In an approach to integrated circuit track coloring, system ground rules, minimum wire width, minimum spacing, and a set of one or more colors, are received. A track layout is created. A first color is assigned to each power track. A second color is assigned to each wide track. One or more legal colors are determined for each minimum width track. A legal color is assigned to each minimum width track.

An exposure mask includes an aligning portion and a boundary portion. The aligning portion may be aligned with pixel areas of a substrate and includes a first exposure member and a second exposure member. The boundary portion includes a first exposure element, a second exposure element, a third exposure element, and a fourth exposure element. The first exposure member, the first exposure element, and the second exposure element are positioned in a first row. The first exposure element is positioned between the first exposure member and the second exposure element and is larger than the second exposure element. The second exposure member, the third exposure element, and the fourth exposure element are positioned in a second row. The third exposure element is positioned between the second exposure member and the fourth exposure element and is smaller than the fourth exposure element. Each exposure member/element includes a light transmitter/blocker.

Disclosed are an array substrate of a thin-film transistor liquid crystal display device and a method for manufacturing the same. The array substrate includes a plurality of data lines, a plurality of dummy data lines, a plurality of first gate lines, a plurality of second gate lines, and a plurality of groups of pixel units. Each group of pixel units includes an odd-numbered column of first thin film transistors and an even-numbered column of second thin film transistors. First ends and second ends of the dummy data lines are connected respectively to two common voltage electrode lines, which are arranged on the substrate in a transverse direction. The method includes steps of: forming a plurality of gate lines and two common voltage electrode lines; forming a source, a drain, and a plurality of data lines; and forming a plurality of pixel electrodes and a plurality of dummy data lines. A light shielding electrode line provided has good voltage driving uniformity.

Embodiments of the present disclosure provide a display panel and a manufacturing method thereof, and a display device. The display panel includes a first substrate and a second substrate that are opposite to each other. The display panel further includes a spacer located on the first substrate, and at least two walls located on the second substrate. The at least two walls form a recess region. The spacer corresponds to the recess region. The at least two walls are configured to limit a movement of the spacer. According to the embodiments of the present disclosure, the spacer is effectively prevented from slipping into the display region when the display panel is subjected to an external force.

A pixel structure comprises: a plurality of pixel units, each: a translucent region including a main translucent region and a sub translucent region disposed adjacent to each other; and a color filter structure disposed in the translucent region, and including a first color filter layer, a second color filter layer, a third color filter layer, a first sub color filter layer disposed oppositely to the first color filter layer, a second sub color filter layer disposed oppositely to the second color filter layer, and a third sub color filter layer disposed oppositely to the third color filter layer; the first color filter layer, the second color filter layer, the third color filter layer disposed in the main translucent region; and the first sub color filter layer, the second sub color filter layer, and the third sub color filter layer disposed in the sub translucent region.

Aspects of the present disclosure address improved systems and methods for generating a clock tree based on route-driven placement of fan-out clock drivers. Consistent with some embodiments, a method may include constructing a spanning tree comprising one or more paths that interconnect a set of clock sinks of a clock net of an integrated circuit device design. The method further includes calculating a center of the set of the clock sinks based on clock sink locations in the integrated circuit device design and identifying a point on the spanning tree nearest to the center of the set of clock sinks. The method further includes generating a clock tree by placing a clock driver at the point on the spanning tree that is nearest to the center of the set of clock sinks.

The present disclosure provides an array substrate and a manufacturing method of the array substrate, a display device. An array substrate comprises: a pixel array, each pixel in the pixel array having a pixel electrode; a transistor array, each transistor in the transistor array having a source electrode; and a connection electrode for electrically connecting the pixel electrode to a corresponding source electrode.