An array substrate and a manufacturing method thereof are disclosed. The manufacturing method includes forming, on a substrate, a first metal pattern layer, a first insulating layer, a second metal pattern layer, and a second insulating layer, successively; coating a photoresist on the second insulating layer; forming a photoresist pattern and an etching protection layer, in a first region of the array substrate, the photoresist pattern exposing a part of the top surface of the second insulating layer, and being coupled to the second insulating layer through the etching protection layer; and performing etching in the first region by using the photoresist pattern as a mask to remove the etching protection layer and at least part of the second insulating layer, without etching the first insulating layer, so as to expose a part of the second metal pattern layer and form a liquid crystal diversion groove.

A display device includes: a first substrate; a gate line on the first substrate, where the gate line extends in a first direction; a data line on the first substrate, where the data line extends in a second direction which intersects the first direction; a thin film transistor connected to the gate line and the data line; a passivation layer on the gate line, the data line and the thin film transistor, where the passivation layer includes a recessed portion; a light blocking portion on the recessed portion of the passivation layer; a main column spacer which protrudes upwardly from the light blocking portion; and a sub-column spacer which protrudes upwardly from the light blocking portion, where the sub-column spacer is spaced apart from the main column spacer.

A display panel and a manufacturing method thereof are provided. The display panel at least includes a metal layer, a pixel electrode arranged on a same layer as the metal layer, a protective layer covering the metal layer and the pixel electrode, and a common electrode disposed on the protective layer. A thickness of the protective layer on the metal layer is greater than a thickness of the protective layer on the pixel electrode.

A display device including: a substrate having display area and a non-display area; and an alignment mark disposed in the non-display area of the substrate. The alignment mark includes a quadrangular-shaped center portion and a plurality of measurement portions that surround the center portion, the plurality of measurement portions including four or more measurement portions, and each of the measurement portions including sides that are parallel with two sides of the quadrangular-shaped center portion.

A mask, a manufacturing method thereof, and a patterning method employing the mask. In the mask, a plurality of masks can be combined into one mask. The pattern area (01) of the mask is provided with a first pattern section (10) and a second pattern section (20) which are not overlapped with each other; light of a first wavelength can run through the first pattern section (10) but light of a second wavelength cannot run through the first pattern section; the light of the second wavelength can run thorough the second pattern section (20) but the light of the first wavelength cannot run through the second pattern section; and the light of the first wavelength and the light of the second wavelength can run through the non-pattern area, or any of the light of the first wavelength and the light of the second wavelength cannot run through the non-pattern area. The mask is obtained by combining a plurality of masks.

The present disclosure provides a mask assembly, a mask apparatus and a mask control method, pertaining to the field of mask technology. The mask assembly includes a mask plate and a controller. The mask plate includes a plurality of mask units. The mask unit has a light transmission state and a light interruption state. The controller is used to control the mask unit to switch between the light transmission state and the light interruption state to adjust a light transmission region of the mask plate. The present disclosure solves the problem that mask efficiency is low. The present disclosure is used to mask film layers.

A COA substrate manufacturing method including: forming a TFT on a base substrate; forming a second insulation layer on the TFT; forming a color resist layer on the second insulation layer; forming a third insulation layer on the color resist layer; forming a through hole which exposes the drain electrode of the TFT; forming an ITO film layer on the third insulation layer; forming a photoresist layer on the ITO film layer; performing a light-shielding process to the photoresist layer on the vias-region ITO film layer and an exposure process to the photoresist layer on the non vias-region ITO film layer; developing the photoresist layer on the vias-region ITO and the non vias-region ITO film layers to obtain a photoresist layer plug covered on the vias-region ITO film layer. The photoresist is provided to fill the through hole so as to improve the quality of a display device.

An active matrix substrate of a liquid crystal panel of an FFS mode includes gate lines, data lines, pixel circuits each including a switching element and a pixel electrode, a protective insulating film formed in a layer over these elements, and a common electrode formed in a layer over the protective insulating film. The data line includes a lower layer conductor part formed using indium tin oxide together with the pixel electrode, and an upper layer conductor part formed using molybdenum niobium and an aluminum alloy. The lower layer conductor part is formed in a disconnected shape at a position of the switching element, and the upper layer conductor part is formed in a continuous shape so as to overlap with the lower layer conductor part. With this, an active matrix substrate capable of preventing a disconnection failure of the data line and an alignment failure is provided.

A method includes a conductive film forming process of forming a conductive film 51 covering a gate insulation film IS and a semiconductor film 42, the gate insulation film 45 covering a gate electrode 37G and a gate line 35G formed on a glass substrate 32 and the semiconductor film 42 formed on the gate insulation film 45 while overlapping the gate electrode 37G, a first etching process of etching the conductive film 51 and forming a source conductive film 46S connected to the semiconductor film 42 and a drain conductive film 46D connected to the semiconductor film 42, a resist forming process performed after the first etching process and forming a resist 53R covering the semiconductor film 42, the source conductive film 46S, and the drain conductive film 46D, and a second etching process performed after the resist forming process and performing etching for removing the conductive film 51 while using the resist 53R as a mask.

This disclosure provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes an organic film layer disposed over a substrate, and is provided with a groove, which is configured for positioning a sealant, extends through the organic film layer, and has an opening on a side opposing to the substrate. The array substrate can further include a sealing film, which covers surfaces of the groove to thereby prevent gas release from the organic film layer.