This disclosure provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes an organic film layer disposed over a substrate, and is provided with a groove, which is configured for positioning a sealant, extends through the organic film layer, and has an opening on a side opposing to the substrate. The array substrate can further include a sealing film, which covers surfaces of the groove to thereby prevent gas release from the organic film layer.

The present disclosure relates to a COA substrate including a glass substrate, a common electrode on the glass substrate, an insulation layer on the common electrode, a data line on the insulation layer, and the data line intersects with the common electrode. The COA substrate further includes a first passivation layer, a RGB color-filter layer, and a second passivation layer arranged on the data line in sequence. A disconnected gap is configured at an intersection of the common electrode and the data line such that the common electrode comprises two opposite ends. The insulation layer fills the gap, and the second passivation layer is configured with a conductive layer spanning over two ends of the common electrode. The present disclosure also relates to a liquid crystal panel including the above COA substrate.

The present invention involves an array substrate structure and a manufacturing method of an array substrate. The manufacturing method of an array substrate, which comprises: Step 1, a substrate is provided, a first metal layer is manufactured on the substrate, and the first metal layer is patterned with a first photo-mask, to manufacture a gate electrode. Step 2, a gate insulating layer is manufactured on the substrate; an active layer is manufactured with a second photo-mask. Step 3, a first via is formed in the gate insulating layer corresponding to the first metal layer with a third photo-mask. Step 4, a second metal layer is manufactured on the gate insulating layer, the second metal layer is patterned with a fourth photo-mask, to manufacture source/drain electrodes, and a second via is formed on where corresponding to the active layer, the first metal layer and the second metal layer are connected at the first via. Step 5, a pixel electrode is manufactured with a fifth photo-mask, the pixel electrode and the source/drain electrodes are directly connected at the second via; the second metal layer is covered and protected by the pixel electrode. The present invention also provides a corresponding array substrate structure. The invention can enhance the aperture ratio of the pixel at high-resolution and the display effect and quality of the liquid crystal display and improve the electrical characteristics of the panel.

The present invention provides a manufacture method of an array substrate and an array substrate manufactured by the method. By employing one mask to achieve the via opening process to the flat layer and the first passivation layer, one mask can be saved to decrease the production cost and to reduce the process time; the conductive connection layer covering the first via on the flat layer and the second via on the first passivation layer are formed at the same time while forming the common electrode, and thus to prevent that the source/the drain and the flat layer to be exposed in the environment for eliminating the possibility that the two generate the reaction, which is beneficial for raising the electrical property of the array substrate and realizing the signal conduction. In the array substrate, the signal transmission is smooth, and the substrate possesses the great electrical property.

A thin film transistor array panel includes a substrate, a data line and a light blocking layer disposed on the substrate, a thin film transistor disposed on the light blocking layer and including a source electrode, a drain electrode, and an oxide semiconductor layer, and an insulating layer disposed on the substrate and including a first contact hole overlapping a portion of the data line, a second contact hole overlapping a portion of the source electrode, and a third contact hole overlapping a portion of the drain electrode, wherein the first contact hole, the second contact hole, and the third contact hole are arranged in a row in a first direction perpendicular to a direction in which the data line is extended.

A display panel and a display terminal are disclosed. display panel. The display panel has a display area and a non-display area on at least one side of the display area. The display panel includes: a first substrate; a first metal layer on the first substrate, the first metal layer including a first metal part disposed in the display area and a second metal part disposed in the non-display area; and a second metal layer on a side of the first metal layer away from the first substrate, the second metal layer including a third metal part in the display area and a fourth metal part in the non-display area.

Embodiments of the present disclosure provide a display panel and a manufacturing method thereof, and a display device. The display panel includes a first substrate and a second substrate that are opposite to each other. The display panel further includes a spacer located on the first substrate, and at least two walls located on the second substrate. The at least two walls form a recess region. The spacer corresponds to the recess region. The at least two walls are configured to limit a movement of the spacer. According to the embodiments of the present disclosure, the spacer is effectively prevented from slipping into the display region when the display panel is subjected to an external force.

A physical layout for a circuit using amorphous metal non-linear resistors as active devices for an in-plane switching liquid crystal display sub-pixel is provided. The lower interconnect of the two amorphous metal non-linear resistors and the lower electrode of the storage capacitor may be concurrently deposited and patterned. The area of the storage capacitor is defined by the overlap of the data signal inter-connect and the storage capacitor lower electrode, which is easily modified through the size of the lower electrode and/or the size of the data signal interconnect where it overlaps the lower electrode and does not degrade the aperture ratio of the pixel. Two embodiments of sub-pixel circuits are described. One, which employs a select line bridge, enables the use of full dot inversion of the image data. The second only allows row inversion of the image data.

Embodiments of the disclosure provide an array substrate and a method for manufacturing the array substrate. The array substrate includes a substrate, a first electrode disposed on the base substrate and a second electrode disposed on the base substrate and located in a different layer from the first electrode with an insulation layer being disposed therebetween, wherein each of the first and second electrodes is a comb-like electrode, and the first and second electrodes are configured to generate an electric field therebetween when being applied with a voltage.

A display device and a method of manufacturing the same are disclosed. The display device includes a lower substrate, subpixels positioned on the lower substrate, and a fine alignment key positioned in at least one of the subpixels. The method of manufacturing the display device includes forming an alignment key outside a target substrate and forming a fine alignment key inside an active area defined as a display area on the target substrate, aligning the target substrate and a mask substrate using the alignment key and the fine alignment key, and performing an exposure operation using the target substrate and the mask substrate.