An operational amplifier operates upon receiving supply of a first voltage and outputs a control voltage on the basis of a reference voltage. A first output transistor has a first electrode connected to a first voltage line that is a supply line for the first voltage; the first output transistor transmits a first current on the basis of the control voltage. An overcurrent protection circuit is connected to the operational amplifier, and includes a resistance unit for adjustment of a temperature coefficient.

An operational amplifier operates upon receiving supply of a first voltage and outputs a control voltage on the basis of a reference voltage. A first output transistor has a first electrode connected to a first voltage line that is a supply line for the first voltage; the first output transistor transmits a first current on the basis of the control voltage. An overcurrent protection circuit is connected to the operational amplifier, and includes a resistance unit for adjustment of a temperature coefficient.

A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and provides an amplified feedback signal to the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first or the second LDO stage. A current limit circuit includes a sense FET coupled to the LDO pass FET, a drain voltage replication circuit coupled between the pass FET and sense FET to provide a sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.

A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and provides an amplified feedback signal to the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first or the second LDO stage. A current limit circuit includes a sense FET coupled to the LDO pass FET, a drain voltage replication circuit coupled between the pass FET and sense FET to provide a sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.

An overcurrent detection device of the present disclosure has two charge storage circuits, a control module and a counter circuit. The control module controls and provides charge paths of the two charge storage circuits, so that the two charge storage circuits are charged by a reference current and a sensed current respectively, wherein the sensed current is generated by an output current of a low-dropout regulator. The counter circuit obtains a voltage of the charge storage circuit charged by the sensed current, and counts accordingly. When the counting of the counter circuit reaches a specific value, the counter circuit outputs an overcurrent detection signal. When the output current is an overcurrent, the counter circuit first counts to the specific value before the charge storage circuit which is charged by the reference current is charged to a specific voltage.

An overcurrent detection device of the present disclosure has two charge storage circuits, a control module and a counter circuit. The control module controls and provides charge paths of the two charge storage circuits, so that the two charge storage circuits are charged by a reference current and a sensed current respectively, wherein the sensed current is generated by an output current of a low-dropout regulator. The counter circuit obtains a voltage of the charge storage circuit charged by the sensed current, and counts accordingly. When the counting of the counter circuit reaches a specific value, the counter circuit outputs an overcurrent detection signal. When the output current is an overcurrent, the counter circuit first counts to the specific value before the charge storage circuit which is charged by the reference current is charged to a specific voltage.

A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and has an output at which an amplified feedback signal is provided to both the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first LDO stage or the second LDO stage. A current limit circuit includes a sense FET having a gate coupled to the gate of the LDO pass FET, a drain voltage replication circuit coupled between the drains of the pass FET and sense FET to replicate the pass FET drain voltage so that the sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.

A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and has an output at which an amplified feedback signal is provided to both the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first LDO stage or the second LDO stage. A current limit circuit includes a sense FET having a gate coupled to the gate of the LDO pass FET, a drain voltage replication circuit coupled between the drains of the pass FET and sense FET to replicate the pass FET drain voltage so that the sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.

A low voltage drop output regulator and a method for controlling thereof for preventing an inrush current that occurs momentarily during an initial operation of a circuit are described. The low voltage drop output regulator includes a differential amplifier configured to output an amplified voltage by comparing a reference voltage with a feedback voltage, a first MOS transistor configured to output an output voltage to a drain terminal by receiving the amplified voltage in a gate terminal, and an inrush preventer connected between a power voltage terminal and a drive node to prevent the inrush current of the first MOS transistor during an initial operation period. The inrush preventer includes a determining unit and a limiter, and the limiter is configured only by a MOS transistor and a switch connected in series between a power voltage terminal and a drive node.

An overcurrent protection circuit configured to limit an output current flowing through an output transistor includes a sense transistor that provides a sense current proportional to the output current, a sense resistor through which the sense current flows, a current limiting circuit that detects a sense voltage generated by the sense resistor and controls a gate voltage of the output transistor, and a current correction circuit that provides the sense resistor with a corrected sense current added to the sense current based on a difference of voltage between a drain voltage of the output transistor and a drain voltage of the sense transistor.