A system on chip (SoC) and an application processor are provided. The SoC includes a memory controller configured to control a memory; a plurality of function modules configured to access the memory through a memory interface; a system interconnect circuit configured to operate based on a first clock signal and connect the memory interface and the plurality of function modules; and a power controller configured to control the first clock signal to be periodically gated, and control the memory to operate in a lower-power mode during a period in which the first clock signal is gated.

A receptacle includes a plurality of universal serial bus (USB) ports including a USB Type C PD port and a USB Type C port couplable to respective devices for charging, a controller coupled to the USB ports and including a dynamic power sharing logic, the controller structured to: determine whether one or more USB ports are coupled to the respective devices and manage first power negotiation and dynamic power sharing if both USB ports are coupled to respective devices or manage second power negotiation if only one USB port is coupled to respective device; an AC/DC converter including a gallium nitride (GaN) MOSFET on at least one of the primary side or the secondary side of the AC/DC converter, the AC/DC converter structured to provide high power to the USB Type C PD port; and a DC/DC converter structured to provide low power to the USB Type C port.

Techniques for reallocating power between a plurality of electronic components and a connection port of a computing system are described. In operation, operational state of an electronic component from amongst multiple electronic components is analysed. Based on the operational state of the electronic component, an unused power available with the electronic components is determined. Based on the availability of the unused power, a default power level associated with the connection port is increased, where the default power level is a predefined power allocated to the connection port for operation.

A technique capable of normally transmitting a LPM token from a transceiver to a USB device is provided. A semiconductor device includes: a controller including a first interface circuit in conformity with UTMI+ standards; a converting circuit including a second interface circuit in conformity with the UTMI+ standards and a third interface circuit in conformity with ULPI standards, the second interface circuit converting data transmitted from the first interface circuit and received, and the third interface circuit transmitting the converted data; a first circuit analyzing a packet output from the controller and identifying and holding a packet identifier contained in the packet; and a second circuit providing a transmission command, after which a data string containing the packet identifier indicating LPM bringing a USB device to a low power consumption state is added, if the first circuit determines that the packet identifier is the LPM.

Systems and methods for using distributed Universal Serial Bus (USB) host drivers are disclosed. In one aspect, USB packet processing that was historically done on an application processor is moved to a distributed USB driver running in parallel on a low-power processor such as a digital signal processor (DSP). While a DSP is particularly contemplated, other processors may also be used. Further, a communication path is provided from the low-power processor to USB hardware that bypasses the application processor. Bypassing the application processor in this fashion allows the application processor to remain in a sleep mode for longer periods of time instead of processing digital data received from the low-power processor or the USB hardware. Further, by bypassing the application processor, latency is reduced, which improves the listener experience.

According to an example of managing a universal serial bus (“USB”), a device connected to a USB hub controller is sensed and a USB information scheme from the device is fetched. A power requirement of the device is determined through the USB information scheme, and a total power consumption of a plurality of devices connected to the USB hub controller is calculated. USB information scheme data to display to a user and a data display arrangement are determined, and a monitor scalar is instructed to display the USB information scheme in the determined data display arrangement. Power to the device is distributed based on the total power consumption of all devices connected to the hub controller and a user setting.

An interface circuit including: a first transmission circuit outputting a first signal to a transmission line via first transfer pads; and a second transmission circuit outputting a second signal to the transmission line via second transfer pads, the first transmission circuit includes a first termination resistor block including a switch and a first termination resistor connected between the first transfer pads, the second transmission circuit includes a second termination resistor block including a switch and a second termination resistor connected between the second transfer pads, and when the first transmission circuit outputs the first signal, the second termination resistor block detects the first signal, and when the first transmission circuit is in a low-power operation mode, the second termination resistor block disconnects the second termination resistor, and when the first transmission circuit is in a high-speed data transfer mode, the second termination resistor block connects the second termination resistor.

A signal transmitter of the invention is coupled to a plurality of signal receivers by a bus, and is configured to transmit display data through the bus for displaying a line. The signal transmitter includes a first data sequence and a second data sequence. The first data sequence has an electronic characteristic of a first value and is transmitted to a first signal receiver of the signal receivers, and the second data sequence has the electronic characteristic of a second value to a second signal receiver of the signal receivers. Wherein, a first signal transmission path from the signal transmitter to the first signal receiver is shorter than a second signal transmission path from the signal transmitter to the second signal receiver, and the first value is larger than the second value.

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.