G06F1/3275

Hybrid memory in a dynamically power gated hardware accelerator

In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.

Managing dynamic temperature throttling thresholds in a memory subsystem
11543970 · 2023-01-03 · ·

Exemplary methods, apparatuses, and systems include a media temperature manager receiving operating temperature measurements for a memory subsystem. The media temperature manager generates an average temperature using the operating temperature measurements. The media temperature manager determines that the average temperature satisfies a first value for a dynamic temperature threshold. The dynamic temperature threshold indicates a temperature at which the memory subsystem throttles media operations. The media temperature manager increases the dynamic temperature threshold to a second value in response to the average temperature satisfying the first value for the dynamic temperature threshold.

Hierarchical Power Management Architecture for SoC-based Electronic Devices
20220413582 · 2022-12-29 ·

An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.

PRECISE POWER CYCLE MANAGEMENT IN DATA STORAGE DEVICES
20220413583 · 2022-12-29 ·

Methods and apparatus for precise power cycle management in data storage devices are provided. One such apparatus is a data storage device that includes a non-volatile memory (NVM) and a processor coupled to the NVM. In such case, the processor is configured to determine a first peak power for a first power phase, operate the DSD at a first DSD power consumption that is less than the first peak power for the first power phase, determine a second peak power for a second power phase based on a residual power equal to a difference between a preselected average power threshold and the first DSD power consumption, and operate the DSD at a second DSD power consumption that is less than the second peak power for the second power phase.

Integrated security system with parallel processing architecture

Methods and systems for managing a premises are disclosed. The premises may comprise a premises management device. The premises management device may be in communication with a security system. The premises management device may manage consumption by maintaining or disabling components associated with the premise management device.

Analog to analog quantizer in crossbar array circuits for in-memory computing
11539370 · 2022-12-27 · ·

Technologies relating to analog-to-analog quantizers with an intrinsic Rectified Linear Unit (ReLU) function designed for in-memory computing are disclosed. An apparatus, in some implementations, includes: a DAC; a first crossbar connected to the DAC; a first analog quantizer connected to the first crossbar; a buffer connected to the first analog quantizer; a second crossbar connected to the buffer; and an ADC connected to the second crossbar.

Shaped and optimized power cycles

Systems and methods, according to the present disclosure, determines a duration of the current queue of commands in the controller, executes all full commands capable of being executed prior to the beginning of a low power cycle. Commands that are not executed may be re-fetched when the device enters a power mode. In an alternate embodiment, a portion of a command that is executable prior to the beginning of a low power cycle is executed, with the un-executed portion of the command being stored on the device, in an “always on” or AON memory. This un-executed portion is fetched and executed when the device enters the power mode.

MEMORY, CHIP, AND METHOD FOR STORING REPAIR INFORMATION OF MEMORY

This application provides a memory, a chip, and a method for storing repair information of the memory. The memory includes a repair circuit that is configured to receive a first signal from a processor and determine to be powered by a first power supply or a second power supply based on a status of the first signal, to store repair information. The repair information is information of the failed bit cells in the memory. The first power supply is zero or in a high impedance state when a system is powered off, and the second power supply is not zero when the system is powered off. The memory further comprises a processing circuit configured to perform communication between the memory and the processor based on the repair information. Therefore, the repair information of the memory can be stored even during power loss.

POWER MANAGEMENT DEVICE AND CONSUMER ELECTRONIC PRODUCT

A power management device and a consumer electronic product are provided. The power management device is for the consumer electronic product. The power management device includes a memory and a controller. The memory stores a power information of a load of the consumer electronic product. An input end of the first voltage regulator is coupled to a power pin of an upstream USB connector, and an output end of the first voltage regulator is coupled to a power end of the load. When USB device is connected to a downstream USB connector of the consumer electronic product, the controller obtains a power demand from the USB device, the controller determines whether to change a power mode of the upstream USB connector according to the power information and the power demand, and the controller controls the second voltage regulator according to the power mode to supply power to the USB device.

ELECTRONIC APPARATUS CAPABLE OF REDUCING STARTUP TIME PERIOD OF DEVICES, METHOD OF CONTROLLING SAME, AND STORAGE MEDIUM
20220404897 · 2022-12-22 ·

An electronic apparatus is capable of reducing the startup time period of a device requiring initialization while suppressing power consumption of a battery. The electronic apparatus includes a main controller, a sub controller, a battery, a power reception controller configured to extract electric power from radio waves, and a power supply controller configured to control supply of electric power from the battery or the power reception controller to the sub controller. The main controller controls supply of electric power to the power supply controller such that electric power is supplied from the battery in a power-on mode in which power consumption of the electronic apparatus is large, and switches the power supply source to the power reception controller when the electronic apparatus shifts to a power-off mode in which the power consumption is smaller than in the power-on mode.