A node interconnection apparatus includes a computing node, a resource control node, and a device interconnection interface connecting the computing node and the resource control node. Each of the computing node and the resource control node includes a processing unit and a storage unit, and the resource control node further includes a resource interface for connecting with a network storage device. The resource control node manages a storage resource of the network storage device, and when the computing node needs to start up, the resource control node obtains operating system startup information from the network storage device and provides the operating system startup information to the computing node. The computing node can start up without the need for storing startup information locally.

Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

An electronic device is provided. The electronic device operates in a normal mode or a low power mode and includes a first non-volatile memory (NVM), a second NVM configured to store first security data generated in the low power mode, and a security processor configured to access the first NVM to store the first security data in the first NVM in the normal mode.

The disclosure relates to a method for enabling the secure functions of a chipset (1) and especially the encryption of the content of the secure memory (7) when the device goes into low power mode. The content of the secure memory (7) may be encrypted and stored in an external memory (20) during low power mode of the chipset (1).

In an electronic device capable of running multiple software applications concurrently, applications, documents, cards, or other activities can be selected for hibernation so as to free up system resources for other activities that are in active use. A determination is made as to which activities should hibernate, for example based on a determination as to which activities have not been used recently or based on relative resource usage. When an activity is to hibernate, its state is preserved on a storage medium such as a disk, so that the activity can later be revived in the same state and the user can continue with the same task that was being performed before the activity entered hibernation.

Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.

The present disclosure includes apparatuses and methods related to modifying an operating mode in memory. An example apparatus can include a memory array and a controller coupled to the memory array, wherein the controller includes a register configured to receive a mode register write command and write a value indicative of an operating mode in which the apparatus has reduced power consumption relative to a normal operating mode.

A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

The present disclosure generally relates to power management for an external storage device. The external storage device includes a power allocation unit coupled to an array of memory devices. A single bridge is present to provide a connection to a host device. The memory devices have operational power states that utilize a first amount of power and non-operational power states that utilize a second amount of power that is less than the first amount of power. The power allocation unit changes the power state of the individual memory devices between operational and non-operational based upon need, but also ensures that the external storage device does not exceed the total power allocation. Thus, the power allocation unit may change a power state of one memory device from operational to non-operational in order to change the power state of another memory device from non-operational to operational.

A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.