Patent classifications
G06F3/0685
READ PERFORMANCE OF MEMORY DEVICES
A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.
Memory management
The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.
Data storage method and apparatus
A data storage method and apparatus are provided. First information of to-be-stored data is first obtained. The first information includes at least one piece of information: a type of the to-be-stored data, a name of the to-be-stored data, and a user identifier corresponding to the to-be-stored data; An expected storage location of the to-be-stored data is determined based on whether the first information of the to-be-stored data meets a condition. At least one data packet in a plurality of data packets of the to-be-stored data is stored in the expected storage location.
Efficient transfers between tiers of a virtual storage system
Efficiently transferring data between tiers in a virtual storage system, including: receiving, by the virtual storage system, a request to write data to the virtual storage system; transforming, within storage provided by a first tier of storage of the virtual storage system, the data to generate transformed data; and migrating, from the first tier of storage to a second tier of storage that is more durable than the first tier of storage of the virtual storage system, at least a portion of the transformed data.
Dynamic size of static SLC cache
Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.
Relaying storage operation requests to storage systems using underlying volume identifiers
Example implementations relate to virtual persistent volumes. In an example, a storage operation request includes a volume identifier. A volume mapping that corresponds to the volume identifier is identified. Underlying volume identifiers are identified based on the volume mapping. The underlying volume identifiers relate to underlying storage volumes that form at least part of a virtual persistent volume associated with the volume identifier. The storage operation request is relayed, using the underlying volume identifiers, to storage systems on which the underlying storage volumes are respectively located.
Machine learning to improve caching efficiency in a storage system
A system and method improve caching efficiency in a data storage system by performing machine learning processes on metadata relating to extents of data blocks, rather than individual blocks themselves. Thus, once the storage devices are divided into extents, various metadata regarding access to the blocks within each extent are aggregated, and per-extent features are extracted. These features are used to train a data regression model that is subsequently used to infer a most likely “hotness” value for each extent at a future time. These predicted values, which may be further classified as e.g. “hot”, “warm”, and “cold” using thresholds, are used to implement the cache replacement policy. Embodiments scale to large and multi-layered caches, and may avoid common caching problems like thrashing, by adjusting the extent size. Policy goal functions may be optimized by dynamically adjusting the classification thresholds.
System data storage mechanism providing coherency and segmented data loading
A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.
Computer system for performing adaptive interrupt control and method for controlling interrupt thereof
A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
Allocating variable media types of memory devices in a memory system
A processing device receives a first instruction specifying that first data is to remain on a first memory device of a plurality of memory devices, the first memory device comprising a first media having a first media type. The processing device further receives a second instruction specifying, based on one or more criteria, that second data is to be moved from the first media having the first media type to a second memory device of the plurality of memory devices, the second memory device comprising a second media having a second media type that is different than the first media type. The processing device further controls the first and second data in the plurality of memory devices based on the first instruction and the second instruction.