A storage unit according to one aspect of the present invention comprises a storage controller and a plurality of storage devices. Each storage device has nonvolatile semiconductor memories serving as storage media. The controller of each storage device diagnoses the state of degradation of the nonvolatile semiconductor memories, and if one of the nonvolatile semiconductor memories is expected to be nearing end of life, then the controller copies the data stored in that degraded nonvolatile semiconductor memory to another nonvolatile semiconductor memory, and then performs shutdown processing for the degraded nonvolatile semiconductor memory, as well as storage capacity reduction processing.

A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.

A system and method for managing garbage collection in Solid State Drives (SSDs) in a Redundant Array of Independent Disks (RAID) configuration, using a RAID controller is described. A control logic can control read and write requests for the SSDs in the RAID configuration. A selection logic can select an SSD for garbage collection. Setup logic can instruct the selected SSD to enter a garbage collection setup phase. An execute logic can instruct the selected SSD to enter and exit the garbage collection execute phase.

According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

A first data item is programmed to a first set of logical units of a memory sub-system. The first set of logical units is associated with a first fault tolerant stripe. A second data item is programmed to a second set of logical units of a memory sub-system. The second set of logical units is associated with a second fault tolerant stripe. A first set of redundancy metadata corresponding to the first data item and a second set of redundancy metadata corresponding to the second data item is generated. A combined set of redundancy metadata is generated based on at least the first set of redundancy metadata and the second set of redundancy metadata. The combined set of redundancy metadata is stored at a specified memory device of the memory sub-system.

According to the present disclosure is provided a device and method for mapping management in a flash memory based on partitioning the memory to a main address space and a substitute space, each partition comprising locations in the memory that are denoted by at least three statues according to which locations are mapped from the main space to the substitute space while responsively modifying the statuses.

A solid state drive (SSD) device includes a first nonvolatile memory package, a second nonvolatile memory package, and a controller. The first nonvolatile memory package includes a first buffer chip and a plurality of first nonvolatile memory chips. The second nonvolatile memory package includes a plurality of second nonvolatile memory chips. The controller controls the first nonvolatile memory package and the second nonvolatile memory package. The first buffer chip communicates a first address signal and a first data with the controller, and selectively communicates the first data with one of the plurality of first nonvolatile memory chips and the plurality of second nonvolatile memory chips based on the first address signal.

A system for communicating over a Controller Area Network (CAN) bus may include a central controller and a plurality of smart devices communicatively coupled with the central controller over the CAN bus and over an identification verification network separate from the CAN bus. Each smart device may be configured to at least one of measure various parameters and control a function based on a command received from the central controller, and then communicate one or more signals indicative of at least one of the measured parameters and the function over the CAN bus to the central controller. Each of the smart devices may include a physical input, a physical output, and at least two nonvolatile memory locations. A first of the at least two memory locations may be configured to store an identifier input signal received at the physical input from at least one of the central controller and an upstream smart device over the identification verification network, the identifier input signal being stored by the smart device as a function instance value for the smart device. The smart device may further include a source address determination module configured to determine a source address for the smart device based on the function instance value and a factory default base address for the smart device, and store the source address in a second of the at least two memory locations.

Methods, systems, and computer readable media can be operable to facilitate the updating of memory at a device based upon a custom command file. In embodiments, update or configuration codes or data may be delivered to a device within a download package, and the download package may include a command file. The command file may identify one or more operations that are to be carried out on the memory of the device, and each respective one of the one or more operations may be associated with a subset or portion of the memory of the device. The device may identify the one or more operations and the one or more associated memory areas from the command file, and the device may carry out the one or more operations on only those areas of the device memory that are identified from the command file as being associated with the operations.

A memory system includes a nonvolatile memory and a controller. The nonvolatile memory has first regions in which data writes and data reads can be executed in parallel. Each of the first regions has second regions which are each a data write/read unit. The controller acquires first values indicating a data write load for each of the first regions, detects a first region having a first value greater than or equal to a first threshold, acquires second values indicating a data write load for each of the plurality of second regions in the detected first region, detects a second region having a second value greater than or equal to a second threshold but less than or equal to a third threshold that is higher than the second threshold, and then move data from the detected second region to a second region in another first region.