Provided are a decoder unit, a decompressor unit, and method for a decoder of multiple stages of adders to decode delta encoded data. A decoder unit implemented in a cache memory having a cache memory cell array comprises a first stage of adder circuits to add, in parallel, pairs of encoded items transformed using a delta encoding, wherein the encoded items include a plurality of deltas of neighbors of sequential source items. The decoder unit further comprises at least one successive stage of adder circuits to add, in parallel in each stage, pairs of outputs from a previous stage of adder circuits, wherein each successive stage has fewer adder circuits than the previous stage, and wherein output from a last of the at least one successive stage comprises the sequential source items.

Provided are a decoder unit, a decompressor unit, and method for a decoder of multiple stages of adders to decode delta encoded data. A decoder unit implemented in a cache memory having a cache memory cell array comprises a first stage of adder circuits to add, in parallel, pairs of encoded items transformed using a delta encoding, wherein the encoded items include a plurality of deltas of neighbors of sequential source items. The decoder unit further comprises at least one successive stage of adder circuits to add, in parallel in each stage, pairs of outputs from a previous stage of adder circuits, wherein each successive stage has fewer adder circuits than the previous stage, and wherein output from a last of the at least one successive stage comprises the sequential source items.

An arithmetic processing device includes: a first multiplier circuit configured to calculate a product DY of an approximate value D obtained by approximating a reciprocal 1/Y of a divisor Y; a dividend operation circuit configured to compare a dividend X and the divisor Y, and generate an operation value twice the dividend X or the operation value equal to the dividend X based on a comparison result; a second multiplier circuit configured to calculate a product of the approximate value D and the operation value as an initial value R(0) of a partial remainder R(n); a third multiplier circuit configured to calculate a product DY*q(n) of the product DY and a partial quotient q(n) that is a predetermined number of upper bits of the partial remainder R(n); and a first addition circuit configured to calculate a new partial remainder R(n) by subtracting the product DY*q(n) from the partial remainder R(n).