Translating text encodings of machine learning models to executable code, the method comprising: receiving a text encoding of a machine learning model; generating, based on the text encoding of the machine learning model, compilable code encoding the machine learning model; and generating, based on the compilable code, executable code encoding the machine learning model.

A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process. The process includes storing each of a plurality of generation instructions in a storage area for each of assembly instructions, the generation instructions instructing the generation of instruction sequences of a first instruction set, each instruction sequence of the first instruction set executing a processing equivalent to each assembly instruction of a second instruction set, identifying a first register that is not used by any of the assembly instructions corresponding to the plurality of generation instructions by referring to the storage area, determining a second register of the first instruction set corresponding to the first register as a temporary register in each of the instruction sequences, and generating the instruction sequence that uses the temporary register.

One or more execution traces of an application are accessed. The one or more execution traces have been collected at a basic block level. Basic blocks in the one or more execution traces are scored. Scores for the basic blocks represent benefits of performing binary slimming at the corresponding basic blocks. Runtime binary slimming is performed of the application based on the scores of the basic blocks.

Systems and methods for configuration management through information and code injection at compile time. An example method comprises: receiving a source code comprising one or more references to a variable; receiving metadata associated with the source code, wherein the metadata specifies a range of values of the variable; and identifying, in view of the range of values of the variable, a reachable section of the source code.

Generation of an executable file derived from a parent executable file having ranges of physical addresses referencing a binary code of at least one core feature (CR), a binary code of a set of native features (F), bytecodes of a set of java features (Pkg), by selecting at least one native feature from the set of native features to be removed, defining the range of physical addresses where the binary code of the selected native feature is stored, selecting at least one java feature from the set of java features to be relocated, and relocating the bytecodes of said at least one selected java feature in the defined range of physical addresses.

The present disclosure provides computer-executable tools which, implemented in a programming language library, may enable source code written using the library to be compiled to object code instrumented for function-level dynamic analysis of memory allocation functions. By tracking heap reads and writes of each target function, symbols may be mapped to memory addresses allocated therefor, and values of input arguments of functions may be mapped to values of output returns. Based on this information, pure functions which embody redundant computations across multiple executions thereof may be identified, while non-pure functions may be screened out. Among pure functions, candidate functions which are executed having the same arguments and returns across multiple executions thereof may be identified, and these functions may be re-compiled to generate object code wherein redundant subsequent executions are avoided, and return values from a first execution thereof are reused across subsequent executions, reducing computational cost.

Disclosed herein are techniques for reducing sizes of executable files. Techniques include identifying an executable file having a plurality of functions; determining, by parsing the executable file or a code structure representing the executable file, that a first and second function each comprise a common block; identifying a third function configured to perform the common block; changing the first and second functions by: removing the common block from at least one of the first or second functions; and inserting a call to the third function into at least one of the first or second functions; and updating the executable file by: replacing, in the executable file, at least one of the first or second functions with at least one of the updated first or second functions; and adding the third function to the executable file.

A method for designing a system on a target device includes generating an intermediate representation of the system from a functional specification of a high-level description of a system. From the high-level description of the system, one or more directives are identified that (1) transform a portion of the system with a specific technique, (2) build a spatial layout for the system by dividing the system according to functionalities, and (3) specialize the system in response to the spatial layout. The intermediate representation of the system is modified in response to the one or more directives.

An information processing apparatus includes: a memory; and a processor configured to: acquire an instruction sequence including plural instructions; generate plural candidates of new instruction sequences capable of obtaining an execution result as same as in the instruction sequence, by replacing at least a part of plural nop instructions included in the instruction sequence with a wait instruction that waits for completion of all preceding instructions; delete any one of the nop instructions and the wait instruction from each of the new instruction sequences, when the execution result does not change in case any one of the nop instructions and the wait instruction is deleted from the new instruction sequences in the candidates; and select a one candidate among the candidates subjected to the delete, the one candidate including the number of instructions equal to or less than a certain number, and having a smallest number of execution cycles.

A method for the generation of a hardware accelerator (20) is described. The method comprises inputting (110) a program (105) with a plurality of lines of code describing an algorithm to be implemented on the hardware accelerator (20) and generating (125) a dataflow graph in memory from the inputted program (105). The dataflow graph is optimized and an output program (140) created from the dataflow graph is output. The output program (140) is then provided to a high-level synthesis tool for generating the hardware accelerator (20).