Apparatuses for data processing and methods of data processing are provided. A data processing apparatus performs data processing operations in response to a sequence of instructions including performing speculative execution of at least some of the sequence of instructions. In response to a branch instruction the data processing apparatus predicts whether or not the branch is taken or not taken further speculative instruction execution is based on that prediction. A path speculation cost is calculated in dependence on a number of recently flushed instructions and a rate at which speculatively executed instructions are issued may be modified based on the path speculation cost.

A computer system includes a branch detection module and a branch predictor module. The branch detection module determines that a first program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a first routine branch is a possible return capable branch having the first routine instruction address that is a detected as being offset. The branch predictor module determines that a second program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a second routine branch is a predicted return branch having a predicted target instruction address based on the NSIA of the second program branch and the predicted offset.

Swapping and restoring context-specific branch predictor states on context switches in a processor. A branch prediction circuit in an instruction processing circuit of a processor includes a private branch prediction memory configured to store branch prediction states for a context of a process being executed. The branch prediction states are accessed by the branch prediction circuit to predict outcomes of its branch instructions of the process. In certain aspects, when a context switch occurs in the processor, branch prediction states stored in a private branch prediction memory and associated with the current, to-be-swapped-out context, are swapped out of the private branch prediction memory to the shared branch prediction memory. Branch prediction states in the shared branch prediction memory previously stored (i.e., swapped out) and associated with to-be-swapped-in context for execution are restored in the private branch prediction memory to be used for branch prediction.

Instructions for execution by a processor in a processor-based system are generated such that multiple compiler generated instruction blocks are provided for a given functional block of source code. Control flow instructions are provided to control the flow of execution between the compiler generated instruction blocks based on runtime information about the processor-based system. By providing multiple compiler generated instruction blocks and the control flow instructions, the one of the compiler generated instruction blocks that will provide the best performance for the processor-based system at the time of execution can be executed. Accordingly, the performance of the processor-based system can be improved.

An apparatus comprises processing circuitry to perform data processing in response to instructions; and a branch predictor to predict a branch outcome for a given branch instruction as one of taken and not-taken, based on branch prediction state information indexed based on at least one property of the given branch instruction. In a static branch prediction mode of operation, the branch predictor predicts the branch outcome based on static values of the branch prediction state information set independent of actual branch outcomes of branch instructions which are executed by the processing circuitry while in the static branch prediction mode. The static values of the branch prediction state information are programmable.

An apparatus comprises processing circuitry to perform data processing in response to instructions fetched from an instruction cache, an instruction prefetcher to speculatively prefetch instructions into the instruction cache, and a branch predictor having at least one branch prediction structure to store branch prediction data for predicting at least one branch property of an instruction fetched for processing by the processing circuitry. On prefetching of a given instruction into the instruction cache by the instruction prefetcher, the branch predictor is configured to perform a prefetch-triggered update of the branch prediction data based on information derived from the given instruction prefetched by the instruction prefetcher. This can help to improve performance, especially for workloads with a high branch density and large branch re-reference interval.

There is provided an apparatus including input circuitry that receives input data. Output circuitry outputs a sequence of instructions to be executed by data processing circuitry, at least some of the instructions being grouped into functions and generation circuitry performs a generation process to generate the sequence of instructions using the input data. The generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation performed during execution of the sequence of instructions and the stored state of control flow speculation is maintained between the functions.

Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor. In misprediction recovery, load-based CI instructions are designated as load-based CI, data dependent (CIDD) instructions if a load-based CI instruction consumed forwarded-stored data of a store-based instruction. During the misprediction recovery, replayed load-based CIDD instructions will reevaluate an accurate source of memory load the correct data instead of consuming potentially faulty data that may have been forwarded by a store-based instruction that may have only existed in a mispredicted instruction control flow path. Limiting the replay of load-based CI instructions to only determined CIDD load-based instructions can reduce execution delay and power consumption in an instruction pipeline.

There is provided input circuitry to receive input data. Output circuitry outputs a sequence of instructions to be executed by data processing circuitry. Generation circuitry performs a generation process to generate the sequence of instructions using the input data with at least some of the instructions being grouped into functions. The sequence of instructions comprises an indirect control flow instruction comprising a field that indicates where a target of the indirect control flow instruction is stored. The target is an entry point to one of the functions and the generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation after execution of the indirect control flow instruction.

Apparatuses for data processing and methods of data processing are provided. A data processing apparatus performs data processing operations in response to a sequence of instructions including performing speculative execution of at least some of the sequence of instructions. In response to a branch instruction the data processing apparatus predicts whether or not the branch is taken or not taken further speculative instruction execution is based on that prediction. A path speculation cost is calculated in dependence on a number of recently flushed instructions and a rate at which speculatively executed instructions are issued may be modified based on the path speculation cost.