An arithmetic processor including a plurality of core groups each including a plurality of cores and a cache unit, a plurality of home agents each including a tag directory and a store command queue and a store command queue. The store command queue enters the received store request to the entry queue in order of reception, the cache unit stores the data of the store request in a data RAM. The store command queue sets a data ownership acquisition flag of the store request to valid when obtaining a data ownership of the store request and issues a top-of-queue notification to the cache control unit when the flag of the top-of-queue entry is valid. In response to the top-of-queue notification, the cache unit update a cache tag to modified state and issue a store request completion notification.

Method and apparatus implementing smart store operations with conditional ownership requests. One aspect includes a method implemented in a multi-core processor, the method comprises: receiving a conditional read for ownership (CondRFO) from a requester in response to an execution of an instruction to modify a target cache line (CL) with a new value, the CondRFO identifying the target CL and the new value; determining from a local cache a local CL corresponding to the target CL; determining a local value from the local CL; comparing the local value with the new value; setting a coherency state of the local CL to (S)hared when the local value is same as the new value; setting the coherency state of the local CL to (I)nvalid when the local value is different than the new value; and sending a response and a copy of the local CL to the requester. Other embodiments include an apparatus configured to perform the actions of the methods.

Method and apparatus implementing smart store operations with conditional ownership requests. One aspect includes a method implemented in a multi-core processor, the method comprises: receiving a conditional read for ownership (CondRFO) from a requester in response to an execution of an instruction to modify a target cache line (CL) with a new value, the CondRFO identifying the target CL and the new value; determining from a local cache a local CL corresponding to the target CL; determining a local value from the local CL; comparing the local value with the new value; setting a coherency state of the local CL to (S)hared when the local value is same as the new value; setting the coherency state of the local CL to (I)nvalid when the local value is different than the new value; and sending a response and a copy of the local CL to the requester. Other embodiments include an apparatus configured to perform the actions of the methods.

According to one embodiment, a cache memory system includes a cache memory and a cache controller. The cache memory can store first data to be read or written by a processor. The cache controller is configured to execute a refresh. The refresh includes reading the first data stored in the cache memory and writing the read first data to the cache memory. When executing the refresh, the cache controller is configured to exchange the first data stored in a first area of the cache memory for second data stored in a second area of the cache memory.

A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.

A processing unit includes a processor core and an associated cache memory. The cache memory establishes a reservation of a hardware thread of the processor core for a store target address and services a store-conditional request of the processor core by conditionally updating the shared memory with store data based on the whether the hardware thread has a reservation for the store target address. The cache memory receives a hint associated with the store-conditional request indicating an intent of the store-conditional request. The cache memory protects the store target address against access by any conflicting memory access request during a protection window extension following servicing of the store-conditional request. The cache memory establishes a first duration for the protection window extension based on the hint having a first value and establishes a different second duration for the protection window extension based on the hint having a different second value.

A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

Techniques of memory inclusivity management are disclosed herein. One example technique includes receiving a request from a core of the CPU to write a block of data corresponding to a first cacheline to a swap buffer at a memory. In response to the request, the method can include retrieving metadata corresponding to the first cacheline that includes a bit encoding a status value indicating whether the memory block at the memory currently contains data of the first cacheline or data corresponding to a second cacheline. The first and second cachelines alternately sharing the swap buffer at the memory. When the decoded status value indicates that the memory block at the first memory currently contains the data corresponding to the first cacheline, an instruction is transmitted to the memory controller to directly write the block of data to the memory block at the first memory.

The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.