In a multi-processor transaction execution environment, a transaction executes a hint instruction indicating proximity to completion of the transaction. Pending aborts of the transaction due to memory conflicts are suppressed based on the proximity of the transaction to completion.

A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

A method of partitioning a set-associative cache for a plurality of software components may comprise identifying a cache height equal to a number of sets in the set-associative cache based on hardware specifications of a computing platform. The method may further comprise determining at least one component demand set of the plurality of software components and dedicating a set in the set-associative cache for the at least one component demand set. The method may further comprise assembling a proportional component sequence of the at least one component demand set having a sequence length equal to an integer submultiple of the cache height. The method may further comprise concatenating assembled proportional component sequences to form a template for mapping a RAM to the dedicated sets in the set-associative cache.

In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

Memory transactions can be tagged with a partition identifier selected depending on which software execution environment caused the memory transaction to be issued. A memory system component can control allocation of resources for handling the memory transaction or manage contention for said resources depending on a selected set of memory system component parameters selected depending on the partition identifier specified by the memory transaction, or can control, depending on the partition identifier specified by the memory transaction, whether performance monitoring data is updated in response to the memory transaction. Page table walk memory transactions may be assigned a different partition identifier to the partition identifier assigned to the corresponding data/instruction access memory transaction.

An adaptive block cache management method and a DBMS applying the same are provided. A DB system according to an exemplary embodiment of the present disclosure includes: a cache configured to temporarily store DB data; a disk configured to permanently store the DB data; and a processor configured to determine whether to operate the cache according to a state of the DB system. Accordingly, a high-speed cache is adaptively managed according to a current state of a DBMS, such that a DB processing speed can be improved.

Systems, apparatuses, and methods for employing system probe filter aware last level cache insertion bypassing policies are disclosed. A system includes a plurality of processing nodes, a probe filter, and a shared cache. The probe filter monitors a rate of recall probes that are generated, and if the rate is greater than a first threshold, then the system initiates a cache partitioning and monitoring phase for the shared cache. Accordingly, the cache is partitioned into two portions. If the hit rate of a first portion is greater than a second threshold, then a second portion will have a non-bypass insertion policy since the cache is relatively useful in this scenario. However, if the hit rate of the first portion is less than or equal to the second threshold, then the second portion will have a bypass insertion policy since the cache is less useful in this case.

A memory device includes a non-volatile memory chip, a connector and a memory controller. The non-volatile memory chip includes an access partition and a hidden partition. The memory controller is used to set first logical blocks mapping to mapping physical blocks in the access partition. The memory controller is used to maintain a first mapping table recording the first logical blocks and the mapping physical blocks. During backup, the memory controller is used to duplicate data in the mapping physical blocks to the hidden partition according to the first mapping table to form backup physical blocks, and establish a second mapping table setting second logical blocks to map to the backup physical blocks. During recovery, the memory controller is used to map the second logical blocks to the backup physical blocks according to the second mapping table for the host system to recover an environment set at the backup operation.