An asynchronous interface according to the disclosure includes: a transmission circuit that transmits, with data of W bits as one word, the data on the one-word basis, and transmits an REQ signal whose value differs by one bit per transmission of the data of one word; a reception circuit including a reception buffer having a reception buffer word count of n (n is an integer of 4 or more), in which the reception circuit receives the data on the one-word basis, and transmits an ACK signal whose value differs by one bit per reception of the data of one word; a data signal line that has a bit width of W, and transfers the data from the transmission circuit to the reception circuit; an REQ signal line that has a bit width of log.sub.2 (n) or more, and transfers the REQ signal from the transmission circuit to the reception circuit; and an ACK signal line that has a bit width of log.sub.2(n) or more, and transfers the ACK signal from the reception circuit to the transmission circuit.

A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.

A method and apparatus for handling outstanding interconnect transactions between a master device and an interconnect component. For example, a transaction intervention module coupled to an interconnect component and a master device of the interconnect component. The transaction intervention module is arranged to receive an indication of a functional state of the master device. If the master device is indicated as being in a faulty functional state the transaction intervention module is further arranged to determine whether any interconnect transactions initiated by the master device with the interconnect component are outstanding. If it is determined that at least one interconnect transaction initiated by the master device is outstanding, the transaction intervention module is arranged to finalize the at least one outstanding interconnect transaction with the interconnect component.

Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method for transmitting data over a serial bus includes receiving from a first line of the serial bus a clock signal used for timing transmission of data on a second line of the serial bus, activating a driver after the first line has transitioned from a first signaling state to a second signaling state while the data is being transmitted on the second line, driving the first line to the first signaling state to transmit a first bit of data when the first bit of data has a first value, and refraining from driving the first line to the first signaling state to transmit a first bit of data when the first bit of data has a second value.

Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

Method and system are disclosed for arbitration of parallel multi-event processing. In one embodiment, a parallel multi-event processing system includes a plurality of hardware components, where each hardware component in the plurality of hardware components is assigned with a unique range of addresses, a plurality of hardware engines, where the plurality of hardware engines are configured to access the plurality of hardware components, a controller configured to perform arbitration on one or more requested transactions among the plurality of hardware engines and the plurality of hardware components based on one or more hardware components in the plurality of hardware components to be accessed, and the plurality of hardware components, the plurality of hardware engines, and the controller are configured to perform the one or more requested transactions according to the arbitration.

Selective insertion of a deadlock recovery buffer in a bus interconnect for deadlock recovery is provided. A bus interconnect is provided that includes router nodes configured to receive new bus transaction messages from agent devices. The router nodes route the received bus transaction messages to other destination router nodes in the bus interconnect to be communicated to designated agent devices. To recover from a deadlock condition when buffers of all router nodes are full, thus halting forward progress of bus transaction messages, a deadlock recovery circuit is provided. The deadlock recovery circuit is configured to detect a bus deadlock condition in the bus interconnect. In response, the deadlock recovery circuit is configured to insert a deadlock recovery buffer that has additional buffer entries in the bus interconnect as another router node to allow forward progress of bus transaction messages to continue to recover from the deadlock condition.

Embodiments for detecting deadlock in a distributed computing environment. Potential deadlocks between resources of nodes in a computing cluster by determining resource reverse pairs of the resources for each transaction from trace or log files using data analytics. The potential deadlocks are identified offline by matching a global or local resource between the nodes in sub-transactions of each transaction as recursively identified from a transaction resource chain.

A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.