The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.

A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a second variable resistor coupled to the clock wire, an analog to digital converter (ADC), and a controller. The data wire is configured to transmit a data signal between a battery and an instrument powered by the battery. The clock wire is configured to transmit a clock signal between a battery and an instrument. The ADC is configured to sample the data signal and the clock signal at a substantially higher frequency than a frequency of the clock signal. The controller is configured to control a resistance of the first variable resistor and a resistance of the second variable resistor based on the digitally sampled data signal and the digitally sampled clock signal.

Disclosed herein is a semiconductor device including a processor that processes input data received via a bus and transmits the process input data as output data via the bus; an input/output data converter that receives the output data via the bus, converts the output data into transmit preGPIO data, and transmits the transmit preGPIO data to the bus; and a GPIO input/output unit that receives the transmit preGPIO data via the bus, converts the transmit preGPIO data into transmit GPIO data, and outputs the transmit GPIO data to at least one GPIO pad.

In one or more embodiments, one or more systems, methods, and/or systems may provide an output signal via a first port of multiple ports; may determine that the output signal is detected via a second port of the multiple ports; if the first port and the second port are not capable of being coupled, may provide a notification that indicates that the first port and the second port are not capable of being coupled; and if the first port and the second port are capable of being coupled: may configure a Serializer/Deserializer (SerDes) associated with the first port to communicate with a SerDes associated with the second port; and may configure a first processor of multiple processors to communicate with a second processor of the multiple processors via the SerDes associated with the first port.

A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a second variable resistor coupled to the clock wire, an analog to digital converter (ADC), and a controller. The data wire is configured to transmit a data signal between a battery and an instrument powered by the battery. The clock wire is configured to transmit a clock signal between a battery and an instrument. The ADC is configured to sample the data signal and the clock signal at a substantially higher frequency than a frequency of the clock signal. The controller is configured to control a resistance of the first variable resistor and a resistance of the second variable resistor based on the digitally sampled data signal and the digitally sampled clock signal.

Methods and devices for controlling frequency of a bus are disclosed. A method may include determining a total-pending load value indicative of a number of a bytes that will pass through the bus in the future and calculating an expected load value based upon i) the total-pending load value, ii) a number of bytes that passed through the bus during a prior time window, and iii) a time duration the bus was active during the prior time window. The frequency of the bus is decreased if the expected load value is less than a lower threshold and increased if the expected load value is greater than an upper threshold. A frequency of the bus is maintained if the expected load value is greater than the lower threshold and less than the upper threshold.

Methods and apparatus for enabling rapid transactions over a speed limited bus are disclosed. In one exemplary embodiment of the present disclosure, a host controller and an application specific integrated circuit (ASIC) are connected via an Inter-Integrated Circuit (I2C) Bus that is further adapted to enable a simplified signaling scheme. Unlike traditional I2C bus transactions which are flexible but speed limited, the simplified signaling scheme reduces bus overhead and enables rapid transactions. In an exemplary context, the simplified signaling scheme enables the ASIC to rapidly configure a series of photodiodes with different channel gain parameters so as to, for example, measure heartbeats by visually detecting a pulse within human flesh.

A method for designing a system on a target device includes generating a timing netlist that reflects timing delays and timing relationships of a base configuration of a block in the system and a target configuration of the block in the system, wherein the base configuration of the block and the target configuration of the block implement different functionalities, and performing synthesis, placement, and routing on the system in response to the timing netlist.

A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Provided are systems and methods for a location-aware, self-configuring peripheral device. In some implementations, the peripheral device may include two or more personalities. In these implementations, a personality enables the peripheral device to provide a service. In some implementations, the peripheral device may be configured to receive a configuration cycle. In some implementations, the peripheral device may further select a personality from among two or more personalities. The peripheral device may use information derived from the configuration cycle to make this selection. Selecting a personality may further include configuring the peripheral device according to the selected personality.