Disclosed are an oxide thin film transistor (TFT), a method of manufacturing the same, and a display panel and a display device using the same, in which a first conductor and a second conductor are provided at end portions of a semiconductor layer formed of oxide semiconductor. The first conductor and second conductor are electrically connected to a first electrode and a second electrode, and covered by a gate insulation layer. The oxide TFT includes a semiconductor layer provided on a buffer and including an oxide semiconductor, a gate insulation layer covering the semiconductor layer and the buffer, a gate electrode provided on the gate insulation layer to overlap a portion of the semiconductor layer, and a passivation layer covering the gate and the gate insulation layer.

A touch sensor integrated type display device includes: a display panel including: pixels connected to data lines and gate lines and division-driven into a plurality of panel blocks, and a plurality of touch sensors connected to the pixels, a display driving circuit providing data of an input image to the pixels in multiple display periods divided from one frame period, and a touch sensing circuit driving the touch sensors and sensing a touch input in a touch sensing period allocated between the display periods of the frame period, adjacent panel blocks being division-driven in the display periods that are separated from each other with the touch sensing period, in which the touch sensors are driven, interposed therebetween, the display driving circuit including a shift register: shifting a gate pulse in accordance with a shift clock timing, and sequentially supplying the gate pulse to the gate lines.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

A display panel control method for a display panel. The display panel includes at least one common electrode line and a plurality of data lines. The method provides a timing control signal including an active interval and a vertical blanking interval. The timing control signal is used to make the display panel either enter the active interval or enter the vertical blanking interval to execute corresponding operation procedures. When the display panel is in the active interval, the method provides corresponding data voltage to every data line according to the image data. When the display panel is in the vertical blanking interval, the method provides a blanking data voltage to every data line. The blanking data voltage is determined according to the polarity of the corresponding data voltage of the corresponding data line and a common voltage of the at least one common electrode line.

A display apparatus includes a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of subpixels. Each of the plurality of subpixels includes a subpixel electrode connected to one of the plurality of gate lines and one of the plurality of data lines through a switching element. A gate driver is configured to output a plurality of gate signals to the plurality of gate lines and to deactivate at least one of the plurality of gate signals in a P-th frame. A data driver is configured to output a plurality of data voltages to the plurality of data lines. Here, P is a positive integer.

A shift register unit and a driving method thereof, a gate driving circuit, and a display device are provided. In the shift register unit, the input circuit inputs an input signal to a first node; the output circuit outputs an output signal to an output terminal; the first control circuit performs a first control on a level of a first control node; the first noise reduction control circuit controls a level of a second node; the second control circuit performs a second control on a level of a second control node; the second noise reduction control circuit controls a level of a third node; the first voltage-stabilizing circuit performs a third control on the level of the second control node, and the second control and the third control cause at least part of the second noise reduction control circuit to be in different bias states.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of onion of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10.sup.−18 A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

A display device includes: pixel electrodes including a first pixel electrode and a second pixel electrode adjacent to the first pixel electrode in a first direction; switching elements including a first switching element coupled to the first pixel electrode and a second switching element coupled to the second pixel electrode; gate lines including a first gate line coupled to the first switching element and a second gate line coupled to the second switching element; a gate driver supplying a gate signal to the gate lines; and drive electrodes including a first drive electrode and a second drive electrode adjacent to the first drive electrode in the first direction. The first drive electrode overlaps the first and second pixel electrodes, and the second gate line. The second drive electrode overlaps the first gate line. The gate driver supplies the gate signal to the first and second gate lines simultaneously.

A gate driver includes a plurality of active stages and a plurality of dummy stages. The active stage is configured to output a plurality of gate signals to a display region. The dummy stage is c connected to respective active stages and configured to output a plurality of dummy carry signals to the respective active stages. The active stage is configured to output the plurality of gate signals and a plurality of active carry signals. The plurality of dummy stages are configured to output the plurality of dummy carry signals, respectively, and not to output any gate signal.