A display device in which high voltage can be applied to a display element is provided. A display element includes a pixel provided with a display element including a pixel electrode and a common electrode, and the pixel is electrically connected to a first data line and a second data line. Supply of a first potential to the pixel through the first data line and supply of a second potential to the pixel through the second data line are performed concurrently, and then a third potential is supplied to the pixel through the second data line, whereby the first potential held in the pixel is changed to a fourth potential, and the fourth potential is applied to the pixel electrode. Here, the second potential is a potential calculated based on the first potential. When the value of the second potential is less than or equal to a potential applied to the common electrode, the third potential is higher than the potential applied to the common electrode. In contrast, when the value of the second potential is greater than or equal to the potential applied to the common electrode, the third potential is lower than the potential applied to the common electrode.

A backplane design for delivering image data in an efficient manner to a memory cell forming a part of a pixel driver comprises a word line design and a column data register release signal delivery design that are speed matched and a complementary bit line delivery design that is speed matched to a row decoder signal circuit operative to pull a word line driver to a state to enable the memory circuits of that row to receive data from the column drivers for each column. The speed matching is effective over a range of operating temperatures because the circuit designs are substantially identical.

A timing controller suitable for receiving image data and a timing signal from a host system and outputting output data to a data driving circuit may include a scrambler configured to output scrambled image data by scrambling the image data; a pattern detection unit configured to calculate a first unbalanced pattern count as a count of unbalanced patterns included in the image data and a second unbalanced pattern count as a count of unbalanced patterns included in the scrambled image data; and an output data determination unit configured to determine output data by using the first unbalanced pattern count and the second unbalanced pattern count.

A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n−4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n−4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.

Provided are a display panel and a display apparatus. In an embodiment, the display panel includes first sub-pixel rows, first gate lines, second sub-pixel rows, and second gate lines. The first sub-pixel row includes sub-pixels arranged along a first direction and is electrically connected to the first gate line. The second sub-pixel row includes sub-pixels arranged along the first direction and is electrically connected to the second sub-pixel row. The second gate line extends along the first direction. A length of the second gate line is smaller than a length of the first gate line. The display panel further includes a gate compensation line electrically connected to the second gate line. The gate compensation line and the second gate line are arranged along the second direction. The gate compensation line and the second gate line are electrically connected to a same second sub-pixel row.

A display substrate has a display area and a peripheral area around the display area. The display substrate includes a plurality of sub-pixels arranged in an array in the display area, and an interface circuit, at least two serial-to-parallel converters and at least one display driver that are in the peripheral area. The interface circuit is configured to receive target data including a plurality of serial display data. A serial-to-parallel converter in the at least two serial-to-parallel converters is used to convert the plurality of serial display data into parallel display data. The serial-to-parallel converter is electrically connected to one display driver to provide the parallel display data to the display driver. The display driver is used to output display driving signals to a plurality of sub-pixels according to the parallel display data.

To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.

A display control circuit applies to a LCoS panel including pixel units and a substrate. The display control circuit includes a pixel memory array circuit and a driving circuit. The pixel memory array circuit includes pixel memory units. A projection of the pixel memory array circuit on the substrate is in a projection of the pixel units on the substrate. The driving circuit includes a row driving circuit and a column driving circuit. A projection of the driving circuit on the substrate is outside the projection of the pixel units on the substrate. The driving circuit provides a modulation signal and pixel data. The pixel memory array circuit modulates the pixel data by the modulation signal to provide a pixel display voltage to each of the pixel units.

The present application discloses a driving circuit, a driving method, and a display panel. The driving circuit includes: a plurality of pixels, each pixel including a first sub-pixel and a second sub-pixel; and a switching circuit, configured to communicate one or both of the first sub-pixel and the second sub-pixel with a scan line and a data line.

A low-power display device is provided. The display device is provided with a plurality of display portions. A data driver circuit and an addition circuit are provided to have a region overlapping with the display portion. First analog data is output from the data driver circuit in the case where first digital data consisting of a first digital value is input to the data driver circuit, whereas second analog data is output from the data driver circuit in the case where second digital data consisting of a second digital value is input to the data driver circuit. The addition circuit generates analog data corresponding to digital data that has a high-order bit that is the first digital value and a low-order bit that is the second digital value, by adding the second analog data to the first analog data. An output terminal of the data driver circuit is directly connected to an input terminal of the addition circuit without through an amplifier circuit.