A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.

A display system comprising a plurality of display controller circuits controlling a like number of independent segments of pixel drive circuits of a backplane. Each pixel drive circuit comprises a memory element and associated pixel drive circuitry. The segments of the backplane may be organized vertically. The word line for the memory cells of a first segment of pixel drive circuits passes underneath a second segment of pixel drive circuits without directly interacting with the pixel drive circuits of the second segment in order to reach the pixel drive circuits of the first segment. The plurality of display controller circuits operate asynchronously but are kept at the same frame rate by an external signal such as Vsync.

Provided is a display device and the like, in which power consumption is reduced in consideration of increased definition of a display image or an increased size of a display panel. In a liquid crystal display device having a power-saving mode in addition to a normal mode, buffers for outputting data signals from a source driver (300) to source lines are made up of positive-polarity buffers (333p) and negative-polarity buffers (333n), and a connection switching circuit 334 is provided between output ends of these buffers and the source driver (300). In the power-saving mode, the buffers (333p, 333n) are connected to source lines by the connection switching circuit (334), while the polarities of the buffers are taken into account, such that the same data signals are applied to two mutually adjacent source lines. Accordingly, although horizontal resolution is halved, half of the buffers in the source driver (300) are halted, thereby enabling great reduction in power consumption.

A display driver backplane, a display device and a fabrication method thereof are disclosed. The display driver backplane includes: a first semiconductor laminate including pixel driver array consisting of a plurality of pixel driver elements and first peripheral circuit unit; first electrode array formed on second surface of first semiconductor laminate; a second semiconductor laminate containing a second peripheral circuit unit, wherein a first surface of the second semiconductor laminate is bonded to a first surface of first semiconductor laminate; and first vias that are formed within first semiconductor laminate and electrically interconnect first-electrode array and pixel-driver array. The present invention addresses prior-art issues of high difficulty in fabricating transistors with different capabilities in the same layer and costly interconnection between transistors in different chips by employing a technique in which two or three chips are stacked together, and hence achieves significant improvements in device performance and reductions in cost.

Provided are a source driver for receiving a digital signal and providing a grayscale signal corresponding to the digital signal and a display device for displaying content. The source driver includes an amplifier configured to provide a grayscale signal, a second driving switch configured to provide the grayscale signal provided by the amplifier to an output node or block the grayscale signal, and a first driving unit including a first switch whose one end is connected to a first voltage and whose other end is connected to the output node and a second switch whose one end is connected to a second voltage and whose other end is connected to the output node, and configured to first drive the output node. The output node is first driven by the first driving unit and then second driven by the amplifier with the grayscale signal.

According to one embodiment, a display device includes a first substrate, a second substrate, a liquid crystal layer, a first alignment film, a pixel electrode, and a common electrode. The liquid crystal layer is disposed between the first substrate and the second substrate. The first alignment film is provided on the first substrate to be in contact with the liquid crystal layer. The pixel electrode is provided on the first substrate and covered with the first alignment film. The common electrode provided on the first substrate to form a lateral electric field. The liquid crystal layer is driven at a frequency of 40 Hz or less. A time constant of the liquid crystal layer is larger than a time constant of the first alignment film.

A display driver includes a gamma correction data transmission unit that transmits a plurality of gamma correction data pieces one by one in each predetermined period. A brightness level indicated by a video signal is converted into a gradation voltage with a gamma characteristic based on the gamma correction data piece transmitted from the gamma correction data transmission unit.

A display device can include a display panel configured to display an image, a scan driving circuit configured to supply a scan signal to the display panel, and a data driving circuit configured to supply a data voltage to the display panel. The data driving circuit can include a data controller configured to vary an output timing of the data voltage based on independent control for each of at least one latch.

Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

A demultiplexer circuit (12) of a display device according to one aspect of the present invention includes signal input lines (Vn), control lines (BSW, GSW, and RSW), and sampling transistors (13R2, 13G2, and 13B1). Sampling transistors connected to one signal input line includes first and second sampling transistors. A first sampling transistor (13B1) includes a control electrode (17) which branches to a first branch part (17a) and a second branch part (17b), either one of an input electrode (15) and an output electrode (18) that are disposed between a first branch part (17a) and a second branch part (17b), and other one of an input electrode (15) and an output electrode (18) that are disposed outside of a first branch part (17a) and a second branch part (17b).