Patent classifications
G09G3/3688
DATA DRIVER AND DISPLAY DEVICE INCLUDING THE SAME
A display device includes a display panel including data lines and pixels electrically connected to the data lines. The data driver supplies data signals to the data lines. The data driver includes: a first output buffer electrically connected to a first data line of the data lines, the first output buffer outputting a first data signal to the first data line; and a first comparator electrically connected to an output terminal of the first output buffer, the first comparator comparing a first slew rate of the first data signal with a first reference slew rate.
HIGH-SPEED DRIVING DISPLAY APPARATUS AND DRIVING METHOD THEREOF
A display apparatus includes a display panel including a plurality of pixels, a timing controller configured to generate current control information on the basis of a degree of transition of image data which is to be applied to a corresponding pixel of the plurality of pixels, and a plurality of output buffers configured to output a target data voltage, corresponding to the image data, to data output channels connected to the plurality of pixels, wherein each of the output buffers includes an amplifier output circuit configured to apply a rising current or a falling current, which is previously set for outputting the target data voltage, to an output node connected to one of the data output channels and a slew rate adjustment circuit configured to selectively and further apply an additional rising current or an additional falling current to the output node on the basis of the current control information, for increasing an output slew rate of the target data voltage.
Larger backplane suitable for high speed applications
A display system comprising a plurality of display controller circuits controlling a like number of independent segments of pixel drive circuits of a backplane. Each pixel drive circuit comprises a memory element and associated pixel drive circuitry. The segments of the backplane may be organized vertically. The word line for the memory cells of a first segment of pixel drive circuits passes underneath a second segment of pixel drive circuits without directly interacting with the pixel drive circuits of the second segment in order to reach the pixel drive circuits of the first segment. The plurality of display controller circuits operate asynchronously but are kept at the same frame rate by an external signal such as Vsync.
DISPLAY DEVICE, DRIVE METHOD FOR DISPLAY DEVICE, AND ELECTRONIC APPARATUS
Display devices and methods are disclosed. In one example, a display device includes display elements arranged in a two-dimensional matrix, data lines for respective display element columns, and a source driver that supplies a video signal voltage to the data lines. In the data lines, display element row includes display elements belonging to first and second groups different from each other. The source driver generates a ramp signal and includes a switch circuit that causes a data line to hold a video signal voltage. When output of the ramp signal and a data line are switched from a connected state to a disconnected state in order to cause the data line corresponding to a certain display element to hold a video signal voltage, a data line corresponding to a display element belonging to a different group and the ramp signal are switched from the disconnected state to the connected state.
LIQUID CRYSTAL DISPLAY DEVICE
A light control panel including an image display region including a region corresponding to an image display region in a display panel and a region corresponding to a peripheral circuit region in the display panel is provided between the display panel and a backlight. A pattern image for controlling radiation of light emitted from the backlight to the display panel is displayed in the image display region in the light control panel according to an action state of the peripheral circuit in the display panel.
Shift register circuit
A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
Display panel and display device applying the same
A display panel and a display device are provided. The display panel includes: a first substrate including a display area and a wiring area, wherein active switches and pixel units are disposed in the display area, and the pixel units couple to the active switches; a second substrate disposed opposite the first substrate; a first drive line portion disposed in the wiring area and including first circuit leads; a second drive line portion disposed in the wiring area and including second circuit leads; a first interface unit connected to the first circuit leads; and a virtual bit interface unit connected to the second circuit leads. The first drive line portion is mounted around the second drive line portion, and the first interface unit is connected to the virtual bit interface unit, so the second drive line portion is coupled to the first drive line portion to form parallel circuits.
Electronic device capable of reducing peripheral circuit area
A display panel includes a first shift register, a first demultiplexer, a plurality of first gate lines, and a plurality of rows of first sub-pixels. The first shift register outputs a first shift signal. The first demultiplexer is coupled to the first shift register and receives the first shift signal and outputs a plurality of first gate driving signals. The plurality of first gate lines receive the plurality of first gate driving signals. Each row of first sub-pixels is coupled to a corresponding first gate line of the plurality of first gate lines. The first sub-pixels of the same row emit light of a same color.
DISPLAY PANEL AND DRIVING METHOD THEREOF
The present application provides a display panel and a driving method of the display panel. The display panel includes an output circuit board having multiple output terminals. The output terminal includes at least two output channels, one of which is electrically connected to one of data lines. At a first moment, a first portion of subpixels in an i-th row receive data signals input from the corresponding data lines. At a second time, a second portion of the sub-pixels in the i-th row excluding the first portion receive data signals input from the corresponding data lines.
Driving method of display panel for reducing viewing angle color deviation and display device
A driving method of display panel and a display device are provided, the driving method includes: taking a time duration of scanning at least two adjacent columns of pixel units as a driving period, a common electrodes of sub-pixels in the pixel units of a preset row are driven by different preset voltages in the current driving period, and the sub-pixels does not need to be driven by doubling the metal wiring and the driving device, thus to achieve the purpose of saving cost; and when the preset voltage is a positive or negative polarity driving voltage, the high voltage sub-pixel and the low-voltage sub-pixel in the pixel unit are driven by a preset driving mode.