A circuit device includes: a selection signal output circuit configured to output a selection signal based on first to fourth driving sequences in demultiplex driving, and a data line driving circuit configured to output first to fourth data signals to a data signal supply line in order of the first to fourth driving sequences. In the first driving sequence, the selection signal output circuit activates an i-th selection signal, and the data line driving circuit outputs an i-th data signal to an i-th data line. At this stage of operation, after the first to fourth driving sequences, a rewriting operation in which the selection signal output circuit activates the i-th selection signal, and the data line driving circuit outputs the i-th data signal to the i-th data line is performed.

A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

A gate driver and a display device including the same, are discussed. The gate driver includes a plurality of stages which are dependently connected to each other. Each of the plurality of pixels includes an output unit which outputs a gate voltage by a voltage of an RQ node, a voltage of a PQ node, and a voltage of a QB node, a first controller which controls the RQ node, a second controller which controls the PQ node, and a third controller which controls the QB node. The gate voltage is configured by a first clock signal having a first phase and a second clock signal having a first phase which is different from the first phase of the first clock signal.

A source driver includes a data latch unit that outputs acquired pixel data, a gradation voltage conversion unit that acquires the pixel data outputted from the data latch unit and converts the pixel data to gradation voltages, an output unit that amplifies and outputs the gradation voltages to source lines, and a timing control unit that controls the timing of the output of the pixel data from the data latch unit. The timing control unit performs control such that the longer a source line is from a source driver to a pixel column, the smaller the timing difference is between acquisition of the pixel data by the data latch unit and the output of the pixel data.

A display device includes a display panel including a plurality of pixels, a gate driver configured to provide gate signals to the plurality of pixels, a data driver configured to provide data signals to the plurality of pixels, a correction data memory configured to store mura correction data, and a controller configured to control the gate driver and the data driver. The controller includes a pattern detection block configured to detect a set pattern in input image data, and a mura correction block configured to perform a mura correction operation that corrects the input image data based on the mura correction data in response to the set pattern not being detected, and to not perform the mura correction operation in accordance with the set pattern being detected.

An image processing circuit is provided. The image processing circuit includes a dither computing circuit and a blending circuit. The dither computing circuit performs a dither computing on the input grayscale data to generate a dithered grayscale data. The blending circuit receives the input grayscale data and the dithered grayscale data, generates a blending weight by comparing the input grayscale data with a first threshold, and performs a blending computing on the input grayscale data and the dithered grayscale data based on the blending weight to output an output grayscale data.

The present invention provides a liquid crystal display panel and an alignment method of the liquid crystal display panel. By inputting a voltage equal to a pixel voltage into data black-matrix less (DBS) electrodes at a gray scale 255, rotation of liquid crystals at the DBS electrodes can be consistent with rotation of liquid crystals at the pixel electrodes during an alignment process. Therefore, the present invention improves brightness at the DBS electrodes of the liquid crystal display panel at the gray scale 255, and increases light transmittance of the liquid crystal display panel.

A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

A liquid crystal display device having an outer shape of a display region formed other than a rectangle. A driver for supplying a video signal is disposed outside the display region. A selector with selector TFT is disposed between the display region and the driver. A video signal line is disposed between the driver and the selector, and a drain line is disposed between the selector and the display region. A scanning circuit for supplying a scanning signal to the scanning line is disposed outside the display region. The selector is disposed between the scanning line and the display region, and covered with ITO as the common electrode. The common bus wiring is disposed outside the selector.

A display device having touch sensors and a method of driving the same are disclosed. The display device includes a display panel including a pixel array including pixels and a touch sensor array including touch sensors formed in the pixel array, the pixel array being divided into blocks, a gate driver to sequentially drive a plurality of gate lines in the pixel array in a block unit, a data driver to drive a plurality of data lines in the pixel array when the gate lines are driven, a touch controller to sequentially drive the touch sensor arrays in the block unit, and a timing controller to divide one frame into at least one display mode at which the pixel array is driven and at least one touch sensing mode at which the touch sensor array is driven and to control the gate drive, the data driver and the touch controller so that the display mode and the touch sensing mode alternate.