A driving controller of a display device, the controller including a segment divider configured to divide the image signal into a plurality of segments and define a predetermined number of adjacent segments among the plurality of segments as a segment block, an image signal adder configured to add up a gray scale value of the image signal of each of the predetermined number of adjacent segments and output the added-up gray scale values, an average gray scale calculator configured to receive the added-up gray scale values and output an average gray scale value, a correction circuit configured to output corrected added-up gray scale values obtained by adding a weight value to each of the added-up gray scale values on the basis of the average gray scale value, and a driving frequency determiner configured to determine the driving frequency of the display device on the basis of the corrected added-up gray scale values.

A display device includes: sub-pixels each including a memory block including memories; memory selection line groups each including memory selection lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a memory selection circuit configured to concurrently output memory selection signals to the memory selection line groups; a potential line; a conduction switch provided for at least one memory in the memory block on a one-to-one basis; and an operating-memory conduction circuit configured to output, to the conduction switch, an operation signal for determining whether to electrically couple or uncouple the potential line and the corresponding one memory. Each memory is capable of storing sub-pixel data therein when being coupled to the potential line. Each sub-pixel displays an image based on the sub-pixel data stored in one memory in the sub-pixel according to the memory selection line supplied with the memory selection signal.

A display panel and driving method, and a display device are provided. The display panel includes a display region and a border region. The display region includes a plurality of data lines extending along a first direction. The border region includes a data output circuit, having an output end electrically connected to a data line. The data output circuit includes at least one gating circuit group and 2L first-gating circuits, where L is a positive integer, and L≥1. One gating circuit group is electrically connected to M data lines, and one first-gating circuit is electrically connected to N data lines, where M=N≥2, and M and N are positive integers, respectively. Each gating circuit group includes a plurality of second-gating circuits, and each second-gating circuit is electrically connected to P data lines, where N>P≥1, and P is a positive integer.

A touch display control circuit, a control method, and an electronic device are provided. The touch display control circuit is configured to drive STN-LCD screens, TN-LCD screens and CSTN-LCD screens. The touch display control circuit includes a display driving circuit and a touch detection circuit. The display driving circuit includes a signal transmission line, multiple groups of signal selection circuits and a reference voltage generation circuit. The signal transmission line is configured to transmit a gate signal and a common signal. The signal selection circuit is configured to select a preset control voltage based on display control timing or touch control timing. The reference voltage generation circuit is configured to provide the preset control voltage. The touch detection circuit is connected to the signal selection circuit and is configured to perform touch detection based on the touch control timing.

A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.

A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.

A digital-to-analog conversion circuit includes: a decoder that, if set to a first selection state, selects two different reference voltages from a reference voltage group on the basis of a digital data signal and outputs the two reference voltages as first and second selection voltages, and if set to a second selection state, selects two reference voltages from the reference voltage group in a manner allowing redundancy and outputs the two reference voltages as the first and second selection voltages; and an amplifier circuit that amplifies and outputs a voltage obtained by averaging a combination of the first and second selection voltages with weighting factors set in advance.

A driving controller of a display device, the controller including a segment divider configured to divide the image signal into a plurality of segments and define a predetermined number of adjacent segments among the plurality of segments as a segment block, an image signal adder configured to add up a gray scale value of the image signal of each of the predetermined number of adjacent segments and output the added-up gray scale values, an average gray scale calculator configured to receive the added-up gray scale values and output an average gray scale value, a correction circuit configured to output corrected added-up gray scale values obtained by adding a weight value to each of the added-up gray scale values on the basis of the average gray scale value, and a driving frequency determiner configured to determine the driving frequency of the display device on the basis of the corrected added-up gray scale values.

A display device includes: sub-pixels each including a memory block including memories; memory selection line groups each including memory selection lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a memory selection circuit configured to concurrently output memory selection signals to the memory selection line groups; a potential line; a conduction switch provided for at least one memory in the memory block on a one-to-one basis; and an operating-memory conduction circuit configured to output, to the conduction switch, an operation signal for determining whether to electrically couple or uncouple the potential line and the corresponding one memory. Each memory is capable of storing sub-pixel data therein when being coupled to the potential line. Each sub-pixel displays an image based on the sub-pixel data stored in one memory in the sub-pixel according to the memory selection line supplied with the memory selection signal.

A display device includes: sub-pixels each including a memory block including memories; memory selection line groups each including memory selection lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a memory selection circuit configured to concurrently output memory selection signals to the memory selection line groups; a potential line; a conduction switch provided for at least one memory in the memory block on a one-to-one basis; and an operating-memory conduction circuit configured to output, to the conduction switch, an operation signal for determining whether to electrically couple or uncouple the potential line and the corresponding one memory. Each memory is capable of storing sub-pixel data therein when being coupled to the potential line. Each sub-pixel displays an image based on the sub-pixel data stored in one memory in the sub-pixel according to the memory selection line supplied with the memory selection signal.