A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

A DRAM including a silicon substrate, buried word lines, and active areas is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas are located on the carrier surface. The buried word lines intersect the active area. Each of the buried word lines has a first width in one of the active area, and has a second width outside the active areas, and the first width is larger than the second width. A manufacturing method of DRAM is also provided.

A DRAM including a silicon substrate, buried word lines, and active areas is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas are located on the carrier surface. The buried word lines intersect the active area. Each of the buried word lines has a first width in one of the active area, and has a second width outside the active areas, and the first width is larger than the second width. A manufacturing method of DRAM is also provided.

Embodiments provide a control circuit and a semiconductor memory. The control circuit includes a bias switching circuit and a first logic gate circuit. The first logic gate circuit includes at least one target transistor. A substrate of one of the at least one target transistor is connected to an output terminal of the bias switching circuit. The first logic gate circuit has a first speed mode and a second speed mode. A transmission speed of the first speed mode is less than a transmission speed of the second speed mode. The bias switching circuit is configured to: receive a target signal, and output a target bias voltage, to increase a threshold voltage of the target threshold. The enabled state of the target signal represents that the first logic gate circuit is in the first speed mode.

Embodiments provide a control circuit and a semiconductor memory. The control circuit includes a bias switching circuit and a first logic gate circuit. The first logic gate circuit includes at least one target transistor. A substrate of one of the at least one target transistor is connected to an output terminal of the bias switching circuit. The first logic gate circuit has a first speed mode and a second speed mode. A transmission speed of the first speed mode is less than a transmission speed of the second speed mode. The bias switching circuit is configured to: receive a target signal, and output a target bias voltage, to increase a threshold voltage of the target threshold. The enabled state of the target signal represents that the first logic gate circuit is in the first speed mode.

A memory system has a configurable mapping of address space of a memory array to address of a memory access command. In response to a memory access command, a memory device can apply a traditional mapping of the command address to the address space, or can apply an address remapping to remap the command address to different address space.

Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.

Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.