A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.

Methods of operating memory might include storing information indicative of a data value of a digit of data stored in a particular memory cell of the memory prior to programming a subsequent digit of data to the particular memory cell, programming the subsequent digit of data to the particular memory cell, monitoring a voltage level of a supply voltage to the memory while programming the subsequent digit of data, and, if the voltage level of the supply voltage falls below a threshold while programming the subsequent digit of data and the information indicative of the data value of the digit of data has a particular logic level, causing a change in threshold voltage of one memory cell of a pair of gate-connected non-volatile memory cells, and inhibiting the other memory cell of the pair of gate-connected non-volatile memory cells from a change in threshold voltage.

A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.

A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.

Disclosed is a data storage circuit that stores target input data inputted to a data input terminal and outputs the stored data as target output data through a data output terminal. The data storage circuit includes a clock control circuit that outputs a master clock signal and a slave clock signal based on a reference clock signal, a master latch circuit that takes the target input data based on the master clock signal, holds the taken data, and outputs the taken data as master output data, a slave latch circuit that takes the master output data based on the slave clock signal, holds the taken data, and outputs the taken data as slave output data, and an output data generation circuit that generates the target output data.

A semiconductor memory device includes a first data input/output (I/O) pad, an X-ray detector and a second data I/O pad. The first data I/O pad receives a test signal. The X-ray detector is connected to the first data I/O pad, includes a bipolar junction transistor (BJT) in which a voltage between an input end and an output end changes according to a cumulative X-ray dosage to the semiconductor memory device, and generates a test result signal indicating the voltage between the input and output ends of the BJT based on the test signal. The second data I/O pad is connected to the X-ray detector and outputs the test result signal.

To provide a semiconductor device that generates a stable negative potential with high accuracy and achieves lower power consumption. The semiconductor device includes a voltage conversion circuit, a comparator, a logic circuit, a transistor, and a capacitor. The voltage conversion circuit has a function of outputting, as a second signal, a signal obtained by conversion of a voltage of an input first signal in response to a clock signal output from the logic circuit. The comparator has a function of being controlled to be supplied with or not supplied with a power supply voltage in response to a power gating signal. The transistor has a function of holding an output voltage of the comparator in the capacitor in a period during which the transistor is in an off state. The logic circuit has a function of switching between supply and stop of the clock signal on the basis of the voltage held in the capacitor in a period during which the power supply voltage to the comparator is stopped.

[Overview] [Problem to be Solved] To provide a non-volatile semiconductor memory that is capable of high-speed writing or reading and suitable for high-density integration. [Solution] A semiconductor device including: a first inverting circuit including n-type FET and p-type FET; a second inverting circuit including n-type FET and p-type FET; a first ferroelectric capacitor; a second ferroelectric capacitor; and a plate line. The second inverting circuit has an output coupled to an input of the first inverting circuit and has an input coupled to an output of the first inverting circuit. The first ferroelectric capacitor has one of electrodes coupled to the input of the first inverting circuit. The second ferroelectric capacitor has one of electrodes coupled to the input of the second inverting circuit. The plate line is coupled to another of the electrodes of the first ferroelectric capacitor and another of the electrodes of the second ferroelectric capacitor.

Power consumption of a semiconductor device is reduced efficiently. The semiconductor device includes a power management unit, a cell array, and a peripheral circuit for driving the cell array. The cell array includes a word line, a bit line pair, a memory cell, and a backup circuit for backing up data in the memory cell. A row circuit and a column circuit are provided in a first power domain capable of power gating, and the cell array is provided in a second power domain capable of power gating. In the operation mode of a memory device, a plurality of low power consumption modes, which have lower power consumption than the standby mode, are set. The power management unit selects one from the plurality of low power consumption modes and performs control for bringing the memory device into the selected low power consumption mode.

A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.