The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus (10) for compensating for radiation tolerance comprises: a voltage value acquisition unit (11) that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit (12) that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit (13) that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.

A semiconductor circuit includes first (IV1, IV3) and second (IV2, IV4) circuits, first (31) and second (32) transistors, a first storage element (35), and a driver (22, 23, 52, 53). The first (IV1, IV3) and second (IV2, IV4) circuits, respectively, apply inverted voltages of voltages at first (N1) and second (N2) nodes to the second (N2) and first (N1) nodes. The first transistor (31) is turned on to couple the first (N1) and third nodes. The second transistor (32) includes a gate coupled to the first node (N1), a drain and a source. One of the drain and the source is coupled to the third node, and another is supplied with a first control voltage (SCL1). The first storage element (35) includes a first end coupled to the third node and a second end supplied with a second control voltage (SCTRL). The first storage element (35) is able to take a first or second resistance state. The driver (22, 23, 52, 53) controls operation of the first transistor (31) and generates the first (SCL1) and second (SCTRL) control voltages.

A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.

A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

Methods of operating memory might include storing information indicative of a data value of a digit of data stored in a particular memory cell of the memory prior to programming a subsequent digit of data to the particular memory cell, programming the subsequent digit of data to the particular memory cell, monitoring a voltage level of a supply voltage to the memory while programming the subsequent digit of data, and, if the voltage level of the supply voltage falls below a threshold while programming the subsequent digit of data and the information indicative of the data value of the digit of data has a particular logic level, causing a change in threshold voltage of one memory cell of a pair of gate-connected non-volatile memory cells, and inhibiting the other memory cell of the pair of gate-connected non-volatile memory cells from a change in threshold voltage.

An electronic circuit comprising an SRAM memory, a control unit, an error detection and correction module and a scrubbing module. The electronic circuit further comprises an integrated SEU monitor of the SRAM memory. The SEU monitor does not use standalone or specialized SRAM memories or particle detectors. Rather, the same SRAM memory that is used for the main operation as a storage element of the electronic circuit serves simultaneously as detector for the SEU monitor. The proposed SEU monitor enables real-time monitoring of the SEU rate in order to detect early the high radiation levels and apply appropriate hardening measures. Furthermore, a method for monitoring an SEU rate and determining permanent faults in an electronic circuit is suggested.

A static random-access memory structure includes a substrate, a first conductive type transistor, a second conductive type transistor and a capacitor unit. The first conductive type transistor and the second conductive type transistor are disposed on the surface of the substrate, and the capacitor unit is positioned between the transistors. The capacitor unit includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode includes a plurality of first protrudent portions and a planar portion. The first protrudent portions are connected to the first planar portion and protrude from the top surface of the planar portion. The second electrode covers the top surface of the first protrudent portions and formed between adjacent first protrudent portions.

Briefly, embodiments of claimed subject matter relate to backup of parameters, such as binary logic values, stored in nonvolatile memory, such as one or more SRAM cells. Binary logic values from a SRAM cell, for example, may be stored utilizing resistance states of a magnetic random-access memory (MRAM) element. Parameters stored in one or more MRAM elements may be restored to SRAM memory cells following a backup.

A voltage regulator and a method for generating a retention voltage for a RAM cell that is sufficiently high to prevent data loss, while minimizing leakage currents are presented. The A voltage regulator is used for generating at least one voltage. The regulator contains mirror circuitry, a leakage device coupled to the mirror circuitry, and a first resistive device coupled to the mirror circuitry via a first output node. The mirror circuitry mirrors a leakage current from the leakage device to the first resistive device, and the leakage current contributes to the generation of a first reference voltage at the first output node.

A random bit cell includes a latch, a voltage selector, a first non-volatile storage element, and a second non-volatile storage element. The latch has a first terminal coupled to a first local bit line, and a second terminal coupled to a second local bit line. The first non-volatile storage element has a first terminal coupled to the first local bit line, and a second terminal coupled to the voltage selector. The second non-volatile storage element has a first terminal coupled to the second local bit line, and a second terminal coupled to the voltage selector. During an initial operation, the first terminals of the first non-volatile storage element and the second non-volatile storage element are floating. During an enroll operation, the first terminals of the first non-volatile storage element and the second non-volatile storage element receive a program voltage from the voltage selector.