A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.

A method of controlling a nonvolatile memory device, includes: determining, based on a write address, whether selected memory cells of the nonvolatile memory device corresponding to the write address are included in an over-erased group; based on the selected memory cells being included in the over-erased group, performing a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells; and after completion of the preprogram operation, performing a data program operation to store write data in the selected memory cells.

A controller of a memory device may determine that an endurance parameter associated with a wear leveling pool of a memory of the memory device satisfies a threshold. The wear leveling pool includes a plurality of memory blocks of the memory. The controller may divide, based on determining that the endurance parameter satisfies the threshold, the plurality of memory blocks of the wear leveling pool into a first wear leveling pool subset that includes a first subset of the plurality of memory blocks and a second wear leveling pool subset that includes a second subset of the plurality of memory blocks. A first subset of a plurality of data partitions is stored in the first subset of the plurality of memory blocks, and a second subset of the plurality of data partitions is stored in the second subset of the plurality of memory blocks.

Disclosed is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit configured to perform an erase characteristic check operation and an erase operation on the plurality of memory blocks. The semiconductor memory device also includes a control logic configured to control the peripheral circuit to perform the erase characteristic check operation and the erase operation, determine whether each of the plurality of memory blocks has a normal erase characteristic or an overerase characteristic according to a result of the erase characteristic check operation for each of the plurality of memory blocks, and set an erase voltage of the erase operation.

A data programming method and a memory storage device are provided. The method includes: programming a plurality of first type physical units in a rewritable non-volatile memory module to store first data; encoding the first data to generate encoded data; receiving second data; and programming at least one of a plurality of second type physical units in the rewritable non-volatile memory module corresponding to the first type physical units to store at least a part of the second data after the first data is encoded. Therefore, the correcting ability for correcting errors in pair physical units in multi-channel programming procedure may be improved.

An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).

A semiconductor device and an erasing method may control a number of times an erase pulse. The erasing method of a flash memory includes the following. Multiple sacrificial memory cells in a block are programmed with different write levels first. When a selected block is erased in response to an erase command, a monitor erase pulse (R1) is applied to a well, and then the sacrificial memory cells are verified (S_EV). When the verification fails, a voltage of the monitor erase pulse is increased and then a monitor erase pulse (R2) is applied until the verification of the sacrificial memory cells passes. When the verification is passed, a normal erase pulse (Q1) is applied to the well based on a voltage of the monitor erase pulse (R2) to erase the selected block.

A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.

A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

A data programming method and a memory storage device are provided. The method includes: programming a plurality of first type physical units in a rewritable non-volatile memory module to store first data; encoding the first data to generate encoded data; receiving second data; and programming at least one of a plurality of second type physical units in the rewritable non-volatile memory module corresponding to the first type physical units to store at least a part of the second data after the first data is encoded. Therefore, the correcting ability for correcting errors in pair physical units in multi-channel programming procedure may be improved.