A data storage device includes a non-volatile memory device, which includes a memory cell array including a plurality of memory cells and a control circuit. Each of the memory cells includes a channel layer, a charge trap layer on the channel layer, and a control electrode on the charge trap layer, the charge trap layer being shared by the memory cells. The charge trap layer includes program regions respectively disposed below the control electrodes of the memory cells, and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes. The control circuit controls the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions.

A storage device is provided. The storage device includes a nonvolatile memory device including a first block and a second block, and a controller including processing circuitry configured to, predict a number of writes to be performed on the nonvolatile memory device using a machine learning model, determine a type of reclaim command based on the predicted number of writes, the reclaim command for reclaiming data of the first block to the second block, and issue the reclaim command.

The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases.

The disclosure further relates to a memory device structured for implementing the above method.

Aspects of a storage device including a memory and controller are provided which allow for erase voltages applied during erase operations to be adaptively changed at elevated temperatures to reduce erase time and prevent erase failures. In response to detecting a lower temperature of the memory, the controller applies a first erase voltage to cells in a block of a die, and in response to detecting a higher temperature of the memory, the controller applies a second erase voltage larger than the first erase voltage to the cells in the block of the die. The controller may apply the different erase voltages depending on whether the temperature of the die falls within respective temperature ranges or meets a respective temperature threshold, which may change for different dies. As a result, successful erase operations at higher temperatures may be achieved.

The present technology relates to a memory device and a method of operating the same. The memory device includes a memory block including a plurality of strings, a peripheral circuit configured to perform an erase operation including a first erase operation, an erase verify operation, and a second erase operation on the memory block, and a control logic configured to control the peripheral circuit to perform the erase operation. During the second erase operation, the control logic controls the peripheral circuit to apply a first erase voltage to a source line of the memory block and apply a second erase voltage, which is lower than the first erase voltage, to a bit line connected to a string determined as erase pass among the plurality of strings.

A processing device sets a first flag that indicates whether a first critical security parameter (CSP) file exists. The first CSP file includes a first set of CSPs for a memory device. The processing device sets a second flag that indicates whether the first CSP file is valid. The processing device sets a third flag that indicates whether a second CSP file exists. The second CSP file includes a second set of CSPs for the memory device. The processing device sets a fourth flag that indicates whether the second critical security parameter file is valid. The processing device selects one of the first or second CSP file as an active CSP file based on an evaluation of the first, second, third, and fourth flags.

A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.

An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

Aspects of a storage device including a memory and controller are provided which allow for erase voltages applied during erase operations to be adaptively changed at elevated temperatures to reduce erase time and prevent erase failures. In response to detecting a lower temperature of the memory, the controller applies a first erase voltage to cells in a block of a die, and in response to detecting a higher temperature of the memory, the controller applies a second erase voltage larger than the first erase voltage to the cells in the block of the die. The controller may apply the different erase voltages depending on whether the temperature of the die falls within respective temperature ranges or meets a respective temperature threshold, which may change for different dies. As a result, successful erase operations at higher temperatures may be achieved.

A memory apparatus and a control method are provided. The memory apparatus includes a non-volatile memory array having plural memory groups, and the control method is applied to the non-volatile memory array. The memory groups jointly share a first well, and the control method is applied to the non-volatile memory array. A first memory group among the memory groups is erased according to a first erase command after the memory apparatus is power-on, and a first amount of the memory groups are recovered in a first erase-recover procedure after the first memory group is erased. A second memory group among the memory groups is erased according to a second erase command after the first erase-recover procedure, and a second amount of the memory groups are recovered in a second erase-recover procedure after the second memory group is erased. The first amount is greater than the second amount.