A non-volatile storage system includes a plurality of non-volatile memory cells configured to form a monolithic three dimensional memory structure, a plurality of bit lines connected to the memory cells, a plurality of source lines connected to the memory cells, a plurality of bit line drivers connected to the bit lines and a plurality of source line drivers connected to the source lines and the bit lines. The source line drivers apply voltages to the source lines based on bit line voltages.

A non-volatile storage system dedicates a subset of blocks to be used for shorting source lines to bit lines at periodic positions along the bit lines during certain memory operations.

A semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

A series of programming pulses, where the individual pulses are identified by a pulse number, is used to program a page of memory cells in parallel. After receiving a pulse, the memory cells under verification are verified to determine if they have been programmed to their respective target states. The memory cells that have been verified are inhibited from further programming while those memory cells not verified will be further programmed by subsequent programming pulses. The pulsing, verification and inhibition continue until all memory cells of the page have been program-verified. Each verify level used in the verification is a function of both the target state and the pulse number. This allows adjustment of the verify level to compensate for changes in sensing, including those due to variation in source line loading during the course of programming.

A semiconductor memory device includes a memory cell includes a charge storage layer, a word line that is connected to a gate of the memory cell, and a controller that performs a write operation on the memory cell by applying a write voltage to the word line, and a verify operation to verify a threshold voltage of the memory cell after the write operation. The verify operation includes a first verify operation using a first verify voltage, and a second verify operation using a second verify voltage higher than the first verify voltage.

A nonvolatile memory device includes a memory cell, and a switching unit. The memory cell includes a cell transistor having a floating gate and a coupling capacitor connected to the floating gate. The switching unit is coupled between the coupling capacitor and a bias terminal, and switches on or off based on the comparison result between a cell current flowing through the memory cell with a reference current during a program operation for programming the memory cell.

Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

A memory device, such as a 3D AND type flash memory, and a compensation method of data retention thereof are provided. The compensation method includes the following. A reading operation is performed on each of a plurality of programmed memory cells of the memory device. Whether a charge loss phenomenon occurs in the programmed memory cells is determined through the reading operation to set the programmed memory cells to be charge loss memory cells. A refill program operation is performed on the charge loss memory cells.

A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells. The control circuit performs a first initialization control of reducing the threshold voltage of both the first memory element and the second memory element of the complementary cell and changing the threshold voltage of at least one of the first memory element and the second memory element at an intermediate level lower than a first writing level and higher than an initialization level, a first writing control of changing the threshold voltage of one of the first memory element and the second memory element of the complementary cell at the first writing level, and a second initialization control of changing the threshold voltage of both the first memory element and the second memory element of the complementary cell at the initialization level.