A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

A method of programming a memory system includes: reading a target page included in a selected memory block in response to a program request when at least one of the pages included in the selected memory block contains data; and performing a program for the target page when, among the data bits included in the data read from the target page, the number of data bits having a first logic value is equal to or less than a preset value.

A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell.

A memory apparatus and method of operation are provided. The apparatus includes memory cells configured to retain a threshold voltage and disposed in memory holes coupled to bit lines and grouped into blocks. A control means is configured to determine an amount of the memory cells of one of the blocks that are programmed based on an electrical current consumed by the memory apparatus during a fourth period of time of a read operation in which selected ones of the bit lines are ramped up to a bit line voltage. The control means adjusts at least one read parameter accordingly. The control means is also configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the data states in the read operation.

A method and apparatus with flash memory control are provided. The method includes performing first programming on a target memory cell of a cell array while adjusting a first programming time and a programming voltage, when a cell current of the target memory cell is determined to satisfy a primary target in association with the first programming, performing second programming on the target memory cell while adjusting a second programming time, and when the cell current of the target memory cell is determined to satisfy a secondary target in association with the second programming, terminating programming on the target memory cell.

A method and apparatus with flash memory control are provided. The method includes performing first programming on a target memory cell of a cell array while adjusting a first programming time and a programming voltage, when a cell current of the target memory cell is determined to satisfy a primary target in association with the first programming, performing second programming on the target memory cell while adjusting a second programming time, and when the cell current of the target memory cell is determined to satisfy a secondary target in association with the second programming, terminating programming on the target memory cell.

A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. The control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.

A memory apparatus and method of operation are provided. The apparatus includes memory cells configured to retain a threshold voltage and disposed in memory holes coupled to bit lines and grouped into blocks. A control means is configured to determine an amount of the memory cells of one of the blocks that are programmed based on an electrical current consumed by the memory apparatus during a fourth period of time of a read operation in which selected ones of the bit lines are ramped up to a bit line voltage. The control means adjusts at least one read parameter accordingly. The control means is also configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the data states in the read operation.

A memory apparatus is provided and includes memory cells configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes each connected to bit lines. Each of the bit lines is coupled to one of a plurality of sense amplifiers arranged in tiers. A control means is configured to program the memory cells in each of a plurality of program iterations of a program operation. The control means counts a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the data states targeted for the memory cells in each of a plurality of verify iterations of a program operation. The count is a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.