A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.

According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.

A memory controller includes an over-program controller that preprograms and then erases the memory cells such that each of the memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage, and a processor that generates fast cell information identifying the fast cells among the memory cells and stores the fast cell information in a buffer. The over-program controller controls the over-programming of the fast cells and normal programming of normal cells among the memory cells based on the fast cell information stored in the buffer.

Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

According to one embodiment, a memory system includes 1st-5th sub-memory regions and a controller, the controller being configured to: calculate a 1st voltage of the 1st sub-memory region in 1st processing; calculate a 2nd voltage of the 4th sub-memory region in 2nd processing; before the 1st processing, use a 3rd voltage when reading the 1st and 2nd sub-memory regions, and the 4th and the 5th sub-memory regions, and use a 4th voltage of the 3rd sub-memory region when reading the 3rd sub-memory region; use the 1st voltage when reading the 1st sub-memory region, use a 5th voltage calculated by using the 1st voltage when reading the 2nd, the 4th, and the 5th sub-memory regions, use a 6th voltage calculated by using the 2nd voltage when reading the 2nd and the 5th sub-memory regions.

Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.

A computer storage device having: a host interface; a controller; non-volatile storage media having memory units of different types and having different program erase budgets; and firmware. The firmware instructs the controller to: generate an address map mapping logical addresses to physical addresses of the memory units the different types; and adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.

A nonvolatile memory device includes multiple memory cells including first memory cells and second memory cells. A method of programming the nonvolatile memory device includes: performing first programming to apply a programming forcing voltage to a bit line of each of the first memory cells; and dividing the second memory cells into a first cell group, a second cell group, and a third cell group, based on a threshold voltage of the second memory cells after performing the first programming. The method also includes performing second programming to apply a programming inhibition voltage to the bit line of each of the first memory cells and a bit line of each of memory cells of the first cell group. A level of the programming forcing voltage is lower than that of the programming inhibition voltage.

An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.

A NAND flash memory including a plurality of levels of cells and a plurality of bitlines. Each bitline corresponds to a plurality of program states, the program states include an Erase-state, a highest state and a plurality of middle states, wherein the bitline voltages of the middle states during programming are between the bitline voltage of the Erase-state and the bitline voltage of the highest state during programming, and the bitline voltages of the middle states during programming are different from each other. The bitline program voltages of middle states of a NAND flash memory are controlled, thus a higher initial programming voltage of wordlines can be set without causing over-programming on the middle states of the bitlines. Therefore, program time is saved, and the programming speed is increased to achieve a fast program function.