NAND flash memory with fast programming function

Abstract

A NAND flash memory including a plurality of levels of cells and a plurality of bitlines. Each bitline corresponds to a plurality of program states, the program states include an Erase-state, a highest state and a plurality of middle states, wherein the bitline voltages of the middle states during programming are between the bitline voltage of the Erase-state and the bitline voltage of the highest state during programming, and the bitline voltages of the middle states during programming are different from each other. The bitline program voltages of middle states of a NAND flash memory are controlled, thus a higher initial programming voltage of wordlines can be set without causing over-programming on the middle states of the bitlines. Therefore, program time is saved, and the programming speed is increased to achieve a fast program function.

Claims

1. A NAND flash memory, comprising: a plurality of levels of cells; a plurality of bitlines, wherein each bitline corresponds to a plurality of program states, the program states include an Erase-state, a highest state and a plurality of middle states, wherein bitline voltages of the middle states during programming are between a bitline voltage of the Erase-state and a bitline voltage of the highest state during programming, and the bitline voltages of the middle states during programming are different from each other; wherein the NAND flash memory is a multi-level cell (MLC) flash memory, and the bitline voltage of the highest state during programming is 0 volt; wherein the plurality of middle states include an A-state and a B-state, the bitline voltage of the A-state during programming is calculated by the formula
VBL=DVA*program loop; wherein DVA and program loop are parameters preset in factory test.

2. The NAND flash memory according to claim 1, wherein the bitline voltage of the B-state during programming is calculated by the formula
VBL=DVA*program loopDVB; wherein DVB is a fixed value preset in factory test.

3. The NAND flash memory according to claim 1, wherein the NAND flash memory is a triple-level cell (TLC) flash memory or a quad-level cell (QLC) flash memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Through reading the detailed description of the following preferred embodiments, various other advantages and benefits will become apparent to those of ordinary skills in the art. Accompanying drawings are merely included for the purpose of illustrating the preferred embodiments and should not be considered as limiting of the application. Further, throughout the drawings, like elements are indicated by like reference numbers.

(2) FIG. 1 is a schematic diagram showing the threshold voltage distribution of a NAND flash memory according to an embodiment of the present invention.

(3) FIG. 2 is a diagram showing the bitline voltage of each state in programming.

(4) FIG. 3 is a schematic diagram showing the bitline voltages of each state of the MLC NAND flash memory.

(5) FIG. 4 is a diagram showing an example of the bitline voltages control.

DETAILED DESCRIPTION OF THE INVENTION

(6) Exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings hereinafter.

(7) FIG. 1 is a schematic diagram showing the voltage distribution of a NAND flash memory according to an embodiment of the present invention. As shown in FIG. 1, in the erase state, the memory cell stores 1, and in the program state, the memory cell stores 0. Between the erase state and the program state, a voltage range between VL and VH is a slow program area (SPA).

(8) FIG. 2 is a schematic diagram showing the bitline voltage in each state corresponding to FIG. 1. As shown in FIG. 2, the bitline voltage level is controlled by a bitline driver, such as the NAND internal circuit for driving the bitline. The bitline voltages are divided into three ranges by the SPA. In the first level below the SPA, the bitline voltage VBL is 0 volt. In the second level within the SPA, the bitline voltage VBL equals to the bitline voltage of SPA, which may be 1.0 volt. In the level above the VH (program verify target level), the bitline voltage may be 2.0 volts. The level above VH is an inhibit bitline area in which bitline cannot be programmed.

(9) FIG. 3 is a schematic diagram showing the bitline voltages of each state of the MLC NAND flash memory. As shown in FIG. 3, and with reference to FIG. 2, in the Erase-state, the bitline voltage VBL equals to VDD such as 2.0 volts, which is the voltage provided by the power source.

(10) In A-state, the bitline voltage VBL during programming is calculated by the formula of:
VBL=DVA*program loop

(11) Wherein DVA is A-state level bitline program voltage, and program loop varies from 0 to N.

(12) In practical application, the parameter of DVA may be given by manufactures, and the bitline voltages VBL in A-state may be obtained according to the parameter DVA and program loop.

(13) In B-state, the bitline voltage VBL during programming is calculated by the formula of:
VBL=DVA*program loopDVB.

(14) Wherein DVB is delta voltage for B-state, and it may be set as a fixed value to guarantee B-state won't be over-programmed. DVB can be fined tune by parameter, and both DVA and DVB are in the range of 1.0-2.0 volts.

(15) FIG. 4 is a diagram showing an example of the bitline voltages control. As shown in FIG. 4, assuming DVA equals to 0.5 V and DVB equals to 0.4V, if program loop is determined, then the bitline voltage of A-state and the bitline voltage of B-state are obtained according to the diagram in FIG. 4.

(16) In C-state, the bitline voltage VBL during programming may be set as zero.

(17) Among the three states of A-state, B-state and C-state, A-state is programmed in the slowest speed, B-state is programmed faster than A-state, but slower than C-state.

(18) As a skilled person should understand, the MLC flash memory and the C-state thereof are just taking as an example. The invention may also be applied to NAND flash memory with a plurality of levels of cells, such as a TLC (triple-level cell) and a QLC (quad-level cell).

(19) The NAND flash memory includes a plurality of bitlines, each bitline corresponds to a plurality of program states, the program states include an Erase-state, a highest state and a plurality of middle states.

(20) The highest state may be the C-state in MLC flash memory, the G-state in TLC flash memory and the 16LC-state in the QLC flash memory. The middle states may be the A-state and B-state of the MLC flash memory.

(21) The bitline voltages of the middle states during programming are between the bitline voltage of the Erase-state and the bitline voltage of the highest state during programming, and the bitline voltages of the middle states during programming are different from each other.

(22) As stated above, the NAND flash memory according to the embodiment of the present disclosure may not be used in MLC flash memory, but may be used in NAND flash memory includes a plurality of levels of cells, such as TLC (triple-level cell) and QLC (quad-level cell) et, al, which is not illustrated thereto.

(23) As stated above, the invention provides a NAND flash memory with a fast programming function. Compared with the conventional technology, the invention controls bitline program voltages of middle states of a NAND flash memory, thus can set higher initial programming voltage of wordlines, therefore over-programming of middle states is avoided, and program time is saved, and the programming speed is increased to achieve a fast program function.

(24) Preferably, the initial programming voltage of wordlines may be set between 12 volts to 13 volts, since the A-state and B-state of the bitline of the MLC flash memory are located in the slow program area, the A-state and B-state will not be over-programmed. As the initial programming voltage of wordlines are rised, the program speed is increased, and fast program function is achieved.

(25) Many details are discussed in the specification provided herein. However, it should be understood that the embodiments of the disclosure may be implemented without these specific details. In some examples, the well-known methods, structures and technologies are not shown in detail so as to avoid an unclear understanding of the description.

(26) It should be noted that the above-described embodiments are intended to illustrate but not to limit the present application, and alternative embodiments may be devised by the person skilled in the art without departing from the scope of claims as appended. In the claims, any reference symbols between brackets form no limit of the claims. The wording include does not exclude the presence of elements or steps not listed in a claim. The wording a or an in front of an element does not exclude the presence of a plurality of such elements. The disclosure may be realized by means of hardware comprising a number of different components and by means of a suitably programmed computer. In the unit claim listing a plurality of devices, some of these devices may be embodied in the same hardware. The wordings first, second, and third, etc. do not denote any order. These wordings may be interpreted as a name.

(27) Also, it should be noticed that the language used in the present specification is chosen for the purpose of readability and teaching, rather than explaining or defining the subject matter of the present application. Therefore, it is obvious for an ordinary skilled person in the art that modifications and variations could be made without departing from the scope and spirit of the claims as appended. For the scope of the present application, the publication of the inventive disclosure is illustrative rather than restrictive, and the scope of the present application is defined by the appended claims.