Various aspects of the present disclosed technology relate to techniques of locating defective memory cells based on scan chain diagnosis. Chain pattern responses of a circuit are first analyzed and at least one or more chain segment defect candidates on one faulty scan chain in the circuit and a fault model associated with the one faulty scan chain are determined. Here, each of the one or more chain segment defect candidates is a counter-based scan chain unit derived from a part or a whole of a memory array. Scan pattern responses are then analyzed to determine one or more memory cell defect candidates in the one or more chain segment defect candidates based on the information of the part or the whole of the memory array and the fault model.

An integrated circuit (IC) is disclosed herein for embedded memory testing with storage borrowing. In an example aspect, an integrated circuit includes a functional logic block, a memory block, and test logic. The functional logic block includes multiple storage units and is configured to store functional data in the multiple storage units during a regular operational mode. The test logic is configured to perform a test on the memory block during a testing mode. The test logic is also configured to retain memory test result data in the multiple storage units of the functional logic block during the testing mode.

Aspects of the disclosure include an integrated circuit (IC) that includes a first input port configured to receive a test pattern, a second input port configured to receive a signature pattern, a set of interconnected circuit elements, and a comparison circuit. The signature pattern is indicative of an expected test output pattern in response to the test pattern. The set of interconnected circuit elements is configured to generate a test output pattern in response to the test pattern being passed through the set of interconnected circuit elements. The comparison circuit is configured to compare the test output pattern to the signature pattern, generate a test result based on a comparison result of the test output pattern to the signature pattern, and output the test result to the test apparatus.

A scan chain circuit is provided. The scan chain circuit includes first and second scan flip-flops and a clock generator. Each of the first and second scan flip-flops has a data-in terminal, a scan-in terminal, a clock terminal, and a data-out terminal. The clock terminals of the first and second scan flip-flop receive first and second clock signals respectively. The data-in terminal of the second scan flip-flop is coupled to the data-out terminal of the first scan flip-flop. During a scan shift cycle of the test mode, an enable pulse of a second clock-enable signal is delayed from an enable pulse of a first clock-enable signal, and the clock generator generates the first clock signal according to the scan clock signal and the first clock-enable signal and further generates the second clock signal according to the scan clock signal and the second clock-enable signal.

Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.

Techniques are presented for determining current leakage from a memory array or other circuit based on a low voltage path. For example, the technique can be applied to determine word line to word line leakage. By looking at a count for the clock used in regulating the low voltage output node, the amount of leakage can be determined. The leakage determination can be performed as part of test process or during normal memory operations.

Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.

A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.

A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.