The present disclosure relates to an apparatus comprising: a host device or a System-on-Chip: a memory component having an independent structure and including at least an array of memory cells organized in sub-arrays with associated decoding and sensing circuitry; a JTAG interface in said at least an array of memory cells including a boundary-scan architecture; an instruction register in said boundary-scan architecture of the JTAG interface including at least a couple of Bits indicative of the presence of a Test Data Input (TDI) signal.

The apparatus has an extended TDI functionality using the data IO to improve the overall performances.

A method for improving the communication between a Host or SoC device and an associated independent memory component is also disclosed.

The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising: a memory array including a plurality of independently addressable sub arrays; sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip; a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access.

A method for retrieving data from the memory component is also disclosed.

The present disclosure relates to a Flash memory portion architecture coupled to a System-on-Chip (SoC) including a matrix of memory cells with associated decoding and sensing circuitry and having a structurally independent structure linked to the System-on-Chip and comprising: a plurality of sub arrays forming the matrix of memory cells; sense amplifiers coupled to a corresponding sub array; a data buffer including a plurality of JTAG cells coupled to the outputs of the sense amplifiers;

The present disclosure relates to an apparatus comprising:

a memory component having an independent structure and including at least an array of memory cells with associated decoding and sensing circuitry and a memory controller;

a host device including multiple cores and coupled to the memory component through at least a communication channel for each corresponding core;

a control and JTAG interface in said at least an array of memory cells;

at least an additional register in said control and JTAG interface for handing data, addresses and control signals provided by the host device and to be delivered to said decoding circuitry and to said controller to perform modify operations.

Testing systems and method of testing an integrated circuit are provided. A testing system comprises an input terminal, multiple circuit elements, each having a register, and an output terminal forming a scan chain through which an input signal is propagated. The testing system further comprises a debugger that includes a mapping module that stores information mapping register values to their respective functional meanings. The input signal is applied to extract all values of all of the registers whether or not accessible by a processor.

The present disclosure relates to apparatuses and methods for memory management and more particularly to a memory device structured with internal analogic measurement mode features.

The memory is provided with means for detecting a correct generation of voltage and/or current reference values in the memory device including at least a memory array and a memory controller. The method provides for a JTAG interface in the memory controller and an analogic measurement block in said memory device driven by said JTAG interface.

Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.

The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.

An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.