Boundary scan test data and a command to initiate a boundary scan test are received via a universal asynchronous receiver-transmitter (UART). Based on receiving the command, a boundary scan test mode is initiated at a memory sub-system controller. A boundary scan test vector based on the boundary scan test data is synchronously streamed to a boundary scan chain. Test result data output by the scan chain is provided to a UART host via the UART.

Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.

A system comprises a testing mode register, a set of pins, and a test access port controller. The test access port controller initiates a first testing mode by configuring the set of pins according to a first pin protocol. The test access port controller configures a first pin to receive first test pattern data based on a first convention and configures a second pin to output first test result data based on the first test pattern data. Based on detecting a register command stored in the testing mode register, the test access port controller initiates a second testing mode by configuring the set of pins according to a second pin protocol. The test access port controller configures the first pin to receive a second test pattern data generated based on a second convention and configures the second pin to output a second test result data based on the second test pattern data.

A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.

A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

A non-volatile computer data storage programming system includes a scan chain modification configured to receive a default model defining a scan chain of an industry standardized device. A controller is in signal communication with the scan chain modification system, and is configured to program an industry standardized device. A non-volatile computer data storage device is configured to receive data from the industry standardized device. The scan chain modification system modifies the default model to generate a new model including a reduced scan chain, and the controller programs the industry standardized device based on the new model such that the industry standardized device is programmed with the reduced scan chain.

A memory is provided with a pre-charge circuit/write driver that pre-charges a bit line in a bit line pair responsive to a master latch output signal from a master latch in a data buffer. A slave latch associated with the master latch is prevented from becoming open by a clock controller during write operations for the memory.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal.

An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.