A memory device to generate intelligent, proactive responses to a read command. For example, signal and noise characteristics of a group of memory cells in a memory device are measured to determine a read voltage. An action is identified based on evaluation of the quality of data retrievable using the read voltage from the group of memory cells. While a response indicating the action is provided responsive to the command, the memory device can initiate the action proactively before a subsequent command, following the response, is received.

A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.

In a method of generating a signal for test in a memory device configured to output a multi-level signal, an operation mode is set to a first test mode. During the first test mode, first data bits included in a plurality of test data are arranged based on a first scheme. Each of the plurality of test data includes two or more data bits. During the first test mode, a first test result signal having two voltage levels is generated based on the first data bits according to the first scheme. The operation mode is set to a second test mode during which second data bits included in the plurality of test data are arranged based on a second scheme. During the second test mode, a second test result signal having the two voltage levels is generated based on the second data bits according to the second scheme.

A memory device to generate intelligent, proactive responses to a read command. For example, signal and noise characteristics of a group of memory cells in a memory device are measured to determine a read voltage. An action is identified based on evaluation of the quality of data retrievable using the read voltage from the group of memory cells. While a response indicating the action is provided responsive to the command, the memory device can initiate the action proactively before a subsequent command, following the response, is received.

A memory device to generate intelligent, proactive responses to a read command. For example, signal and noise characteristics of a group of memory cells in a memory device are measured to determine a read voltage. An action is identified based on evaluation of the quality of data retrievable using the read voltage from the group of memory cells. While a response indicating the action is provided responsive to the command, the memory device can initiate the action proactively before a subsequent command, following the response, is received.

A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In-system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.

A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, the package test, the module test or the mounting test is failed.

A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, the package test, the module test or the mounting test is failed.

Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.

An electronic device includes a pattern data generation circuit and a data input/output (I/O) circuit. The pattern data generation circuit generates pattern data having a serial pattern based on a command/address signal. The data I/O circuit outputs the pattern data or read data as internal data based on a read command for a read operation and an internal command in a test mode. The data I/O circuit receives and stores the internal data, which are output, as write data for a write operation.