An electronic device includes a pattern data generation circuit and a data input/output (I/O) circuit. The pattern data generation circuit generates pattern data having a serial pattern based on a command/address signal. The data I/O circuit outputs the pattern data or read data as internal data based on a read command for a read operation and an internal command in a test mode. The data I/O circuit receives and stores the internal data, which are output, as write data for a write operation.

A memory device includes: a plurality of sense amplifier circuits sensing a data bit in response to a parallel test signal from a plurality of banks; a plurality of comparators comparing the data bit from each of the plurality of sense amplifier circuits with a test bit; and a logic circuit receiving output signals of the plurality of comparators and outputting a test result, wherein each of the plurality of comparators receives the test bit, an evolved parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bit and the test bit in response to the evolved parallel bit test (PBT) signal, the at least one logic state test setting signal, and the test pass signal, and passes a corresponding bank regardless of a test operation in response to the test pass signal.

A memory device includes: a plurality of sense amplifier circuits sensing a data bit in response to a parallel test signal from a plurality of banks; a plurality of comparators comparing the data bit from each of the plurality of sense amplifier circuits with a test bit; and a logic circuit receiving output signals of the plurality of comparators and outputting a test result, wherein each of the plurality of comparators receives the test bit, an evolved parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bit and the test bit in response to the evolved parallel bit test (PBT) signal, the at least one logic state test setting signal, and the test pass signal, and passes a corresponding bank regardless of a test operation in response to the test pass signal.

The present disclosure relates to a memory device comprising a memory array and a periphery circuitry configured to read data from and/or write data to the memory array, wherein the periphery circuitry comprises a programmable circuitry causing the memory device to access data stored in the memory array in accordance with manifest loop instructions. The programmable circuitry comprises a control logic configured to control the operation of the periphery circuitry in accordance with a set of parameters derived from the manifest loop instructions. The present disclosure further relates to a method for controlling the operation of a memory device and to a processing system comprising the memory device.

An integrated circuit for outputting a function value, comprising a pattern matching circuit, configured to compare an input value and multiple transformed versions of the input value with a specified bit pattern, wherein the transformed versions of the input value or the specified bit pattern are created by repeated application of a transformation to the input value or the specified bit pattern, wherein the function is invariant under the transformation or wherein an inverse transformation exists for the transformation, by means of which a change in the function values that is caused by the transformation of the input values can be reversed, a selection circuit configured to select a function value depending on the matching result of the pattern matching circuit and the input value, and an output circuit configured to output a function value for the input value based on the selected function value.

A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.

In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; when one of the first bit value and the redundant bit values do not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values; and asserting a flag signal when the majority bit value does not match the first write value.

In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; when one of the first bit value and the redundant bit values do not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values; and asserting a flag signal when the majority bit value does not match the first write value.

A memory device includes: a plurality of sense amplifier circuits sensing a data bit in response to a parallel test signal from a plurality of banks; a plurality of comparators comparing the data bit from each of the plurality of sense amplifier circuits with a test bit; and a logic circuit receiving output signals of the plurality of comparators and outputting a test result, wherein each of the plurality of comparators receives the test bit, an evolved parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bit and the test bit in response to the evolved parallel bit test (PBT) signal, the at least one logic state test setting signal, and the test pass signal, and passes a corresponding bank regardless of a test operation in response to the test pass signal.

A memory device to generate intelligent, proactive responses to a read command. For example, signal and noise characteristics of a group of memory cells in a memory device are measured to determine a read voltage. An action is identified based on evaluation of the quality of data retrievable using the read voltage from the group of memory cells. While a response indicating the action is provided responsive to the command, the memory device can initiate the action proactively before a subsequent command, following the response, is received.