A method includes injecting scan patterns into an input of a decompressor that distributes the scan patterns to a plurality of scan chains whose outputs are coupled to inputs of a compressor, which provides a compressed scan test result representing the plurality of scan chains. The method also includes, in response to the compressed scan test result being indicative of failure, identifying a particular scan chain of the plurality of scan chains that is responsible for the failure by a debug circuit that is coupled to the input of the decompressor and to a compressor output. The debug circuit enables an output of any single scan chain of the plurality of scan chains to be available at the compressor output while suppressing outputs of all other scan chains of the plurality of scan chains.

An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.

The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.

Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I/O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.

A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.

The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains. The operational mode information comprising information of the full-toggle scan chains may be determined based on reduced toggle ranges first and the hold-toggle pattern may then be determined using a relaxation method. Alternatively, the hold-toggle pattern and the full-toggle scan chains may be determined incrementally together.

A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.