A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.

A method and circuit for implementing enhanced scan data testing with decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) testing through scan skewing, and a design structure on which the subject circuit resides are provided. The circuit is divided into multiple chiplets. Each chiplet includes a stump mux structure including multiple stump muxes connected in series, and a respective chiplet select is provided on shared scan inputs to respective chiplets. The chiplet select gates scan clocks, and when a chiplet is not selected the chiplet retains its data. The chiplet select enables test data to be skewed as scan data enters each chiplet.

A test apparatus and a test method for testing a plurality of blocks in a circuit, the plurality of blocks having identical structures. The test apparatus includes a comparing device, configured to collect output responses generated by the plurality of blocks by applying an excitation signal to the plurality of blocks in parallel, compare the output responses of the plurality of blocks to determine whether the output responses of the plurality of blocks are identical, and output results of the comparison of the comparing device; and a determining device, configured to receive the results of the comparison of the comparing device, and determine whether the plurality of blocks have a defect according to the results of the comparison of the comparing device.

A semiconductor device addresses to a problem in which a current consumption variation rate increases during BIST execution causing resonance noise generation in a power supply line. The semiconductor device includes a self-diagnosis control circuit, a scan target circuit including a combinational circuit and a scan flip-flop, and an electrically rewritable non-volatile memory. A scan chain is configured by coupling a plurality of the scan flip-flops. In accordance with parameters stored in the non-volatile memory, the self-diagnosis control circuit can change a length of at least one of a scan-in period, a scan-out period and a capture period, and can also change a scan start timing.

This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.

An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.

A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

A distributed test circuit includes partitions arranged in series to form a scan path, each partition including a scan multiplexer, a test data register, and a segment insertion bit component. The scan multiplexer of each partition provides inputs to the corresponding test data register of the each partition. Broadcast control logic generates a select signal to the scan multiplexer of each partition to place the test circuit in a broadcast mode when the select signal is asserted, and to switch the test circuit to a daisy mode when select signal is de-asserted. The segment insertion bit is operable to include or bypass each partition from the scan path.

A number of embodiments include an apparatus comprising a memory array including a first memory bank and a second memory bank and a serializer/de-serializer coupled to the first memory bank and the second memory bank. The serializer/de-serializer may be configured to receive a scan vector from the first memory bank, send the scan vector to a device under test, receive scan test responses from the device under test, and send the scan test responses to the second memory bank. Scan control logic may be coupled to the serializer/de-serializer and the device under test. The scan control logic may be configured to control operation of the serializer/de-serializer and send a scan chain control signal to the device under test, wherein the scan chain control signal is to initiate performance of a scan chain operation using the scan vector.

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.