An integrated circuit includes a logic circuit block that includes a first adaptive logic module configurable to store a first state of a first signal received from a device-under-test in a first register, a second adaptive logic module configurable to store a second state of a second signal in a second register during a user mode of the integrated circuit simultaneously with the first state of the first signal being stored in the first register, and a third adaptive logic module configurable to store a third state of the first signal in a third register. The first and the third states of the first signal are stored for consecutive clock cycles in the first register and the third register. The logic circuit block is configurable to scan out the second state in the second register and the third state in the third register.

A method for circuit design includes providing one or more wrapper cells for use with a library of standard cells in design of an IC. Each wrapper cell has geometrical dimensions matching a corresponding group of one or more of the standard cells and defines an electrical path, including at least one via, from a location of a terminal in a lower metal layer in the standard cells in the corresponding group to a location in an upper metal layer. A computerized place-and-route tool receives a layout of the IC including a wrapper cell superimposed over one of the standard cells in the corresponding group. The place-and-route tool automatically routes a signal connection through the upper metal layer and the at least one via defined by the superimposed wrapper cell to the predefined signal terminal in the lower metal layer in the one of the standard cells.

Various aspects of the disclosed technology relate to techniques of selecting scan cells from state elements for partial scan designs. Signal probability values for logic gates in a circuit design are first determined. Based on the signal probability values, next-state capture probability values for state elements in the circuit design are computed. Based on the next-state capture probability values, scan cells are selected from the state elements. Scan cells may be further selected based on continuously-updated control weight values and observation weight values associated with the state elements.

A method for circuit design includes providing one or more wrapper cells for use with a library of standard cells in design of an IC. Each wrapper cell has geometrical dimensions matching a corresponding group of one or more of the standard cells and defines an electrical path, including at least one via, from a location of a terminal in a lower metal layer in the standard cells in the corresponding group to a location in an upper metal layer. A computerized place-and-route tool receives a layout of the IC including a wrapper cell superimposed over one of the standard cells in the corresponding group. The place-and-route tool automatically routes a signal connection through the upper metal layer and the at least one via defined by the superimposed wrapper cell to the predefined signal terminal in the lower metal layer in the one of the standard cells.

A system for using different scan chains to test differential circuit and a method thereof are disclosed. In the system, two scan chains are set up for two electronic components on a target circuit board, and test data for the two scan chains are sequentially pushed to the two scan chains respectively according to a data flow direction between the two scan chains, and after the electronic components output result data, a test result can be determined according to the test data for the two scan chains and the result data. This testing manner can be performed on all electronic components, so as to achieve the technical effect of stably performing differential signal test on all electronic components of the target circuit board.

An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.

An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.

Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row.

Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG.

A scan reset control circuit includes a single scan reset input configured to receive a reset signal, a plurality of scan reset outputs configured to be coupled to a plurality of circuit blocks in a one-to-one ratio, a plurality of writable non-scan test data registers including register outputs configured to assert or deassert the reset signal, and a plurality of reset enable circuits coupled to the plurality of scan reset outputs in a one-to-one ratio. Each of the scan reset outputs is configured to simultaneously reset a set of scan flip-flops of the corresponding circuit block. Each of the plurality of reset enable circuits includes an input coupled to the single scan reset input, a selector input coupled to the register outputs, and an output coupled to the corresponding scan reset output.