G01R31/3191

Apparatus and method of monitoring chip process variation and performing dynamic adjustment for multi-chip system by pulse width
11789076 · 2023-10-17 · ·

A multi-chip system includes a plurality of chips and a monitoring and calibration system. The plurality of chips include at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via a chip-to-chip connection, the first chip transmits an output signal to the second chip via the chip-to-chip connection, and the second chip processes an input signal that is derived from the output signal transmitted via the chip-to-chip connection. The monitoring and calibration system calibrates a chip setting of at least one of the first chip and the second chip for pulse width calibration of the input signal.

REMOVING EFFECTS OF INSTABILITIES OF MEASUREMENT SYSTEM
20210341526 · 2021-11-04 ·

A measurement system and a method of removing effects of instability of the measurement system while measuring at least one S-parameter of a device under test (DUT) are provided. The method includes initially determining a characteristic of the measurement system, including identifying a location of an instability in the time domain of the measurement system; determining a change of the characteristic of the measurement system while connected to the DUT; and compensating for the determined change of the characteristic of the measurement system while connected to the DUT by removing effects of the determined change on measurements of the at least one S-parameter of the DUT.

Calibration arrangement and method for deriving a resistance of a resistor
11162990 · 2021-11-02 · ·

A calibration arrangement for calibrating a power source includes first and second resistors with first and second resistances, respectively, which are usable in calibrating the power source. The second resistance is smaller than the first resistance and the calibration arrangement is configured to allow for a measurement of the first resistance of the first resistor. The calibration arrangement is configured to form a series connection of the first resistor and of the second resistor, to allow for at least two voltage measurements between at least two different pairs of circuit nodes of the series connection, wherein a same current is applied during the at least two voltage measurements, and to derive the second resistor with a second resistance on the basis of the at least two voltage measurements and a result of the measurement of the first resistance of the first resistor.

CIRCUIT FOR CONTROLLING CALIBRATION, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING CALIBRATION

A circuit for controlling calibration includes a process circuit, an off-chip calibration circuit and a mode switching circuit. The process circuit is configured to perform, in a first test mode, a process corner test on the memory to obtain a test result signal, the test result signal being used for determining a process corner parameter. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a controller, the first calibration code being determined by the controller according to a current environment parameter of the memory and the process corner parameter.

AUTOMATED VERIFICATION OF INTEGRATED CIRCUITS
20230076636 · 2023-03-09 ·

Embodiments of the present disclosure pertain to techniques for generating and/or verification of integrated circuits. In one embodiment, parameters of a circuit to be generated are used to automatically generate customized test programs. In another embodiment, an integrated circuit comprises circuits to facilitate testing and controlling test coverage. In yet another embodiment, data obtained from physical circuits is used to generated or modify customized predefined behavioral models of functional circuit components having particular parameters.

Multi-channel timing calibration device and method

A multi-channel timing calibration device and a method applicable thereto are provided. The device includes: a plurality of channel inputs, at least one relay switch, at least one comparator, at least one first multiplexer, and a time measurement chip. The at least one comparator is connected to the at least one relay switch, and connected to a reference voltage or a digital analog converter. The at least one first multiplexer has different signals for different channel groups and outputs a signal of a designated channel. The time measurement chip calculates a timing difference of each of the channels of each of the channel inputs as a basis for delay of the timing signals.

Circuit measuring device and method

A circuit measuring device and a method thereof are provided. A voltage source supplies a common voltage such that a calibration current having a preset current value flows from a current-voltage converter to a final test machine. The current-voltage converter converts the calibration current into a calibration voltage. At this time, a voltage sensing component senses a voltage between an input terminal and an output terminal of the current-voltage converter to output sensed calibration data. The current-voltage converter converts a tested current outputted by a tested circuit into a tested voltage. At this time, the voltage sensing component senses the voltage between the input terminal and the output terminal of the current-voltage converter to output actual sensed data. When the final test machine determines that a difference between the sensed calibration data and the actual sensed data is larger than a threshold, the tested circuit is adjusted.

SYSTEMS AND METHODS FOR STORING CALIBRATION DATA OF A TEST SYSTEM FOR TESTING A DEVICE UNDER TEST
20220260633 · 2022-08-18 ·

Embodiments of the present invention provide systems and methods for storing calibration data for a test system operable to test a device under test (DUT). The test system includes one or more channel modules and a device interface. A first part of the calibration data is stored on a non-volatile memory. The non-volatile memory can be disposed in different parts of the test system. The non-volatile memory is located on the device interface and can also be located on one or more of the channel modules, as well as an attachment of the test system. The non-volatile memory is associated with the one or more channel modules. The second part of the calibration data is stored on a non-volatile memory associated with the device-under-test interface.

METHOD FOR TESTING A DEVICE UNDER TEST
20220206067 · 2022-06-30 ·

A method for testing a device under test, the device under test being a measuring instrument to measure a physical parameter of a fluid, includes: performing a plurality of valid test runs, wherein a valid test run includes: exposing the device under test and a reference measuring instrument to the fluid under a set of influences, the set of influences being defined by influence parameters; monitoring the influence parameters; obtaining a reference value for the physical parameter from the reference measuring instrument; and obtaining a test value for the physical parameter from the device under test, wherein a test run is invalidated if influence parameters do not meet specified test requirements for the influence parameters; and then evaluating a plurality of test values originating from the plurality of valid test runs with respect to at least one of accuracy, repeatability and reproducibility.

Test system and the method for testing a semiconductor device
11385276 · 2022-07-12 · ·

A test system includes: an input signal generation unit that generates an input signal that drives a semiconductor device as a test target; a reference signal generation unit that supplies a reference signal, which is for use in generating the input signal, to the input signal generation unit; and a detection unit that, while implementing a test of the semiconductor device, generates a standard signal in which the same signal output as an output of the reference signal output from the reference signal generation unit is expected, and outputs a detection unit output signal based on the reference signal and the standard signal.