Embodiments of the disclosure provide a method and device for testing an integrated circuit (IC). Calibration parameters of test boards are determined respectively by acquiring identification information of the test boards, and then each of to-be-tested devices in each of the test boards is tested respectively based on the calibration parameters of the test boards. According to the embodiments of the disclosure, the calibration parameters of the test boards are determined respectively according to the identification information corresponding to the test boards, therefore when different types of test boards are adopted by a test machine, each type of test boards may acquire the accurate calibration parameter, so that the accuracy of a test result is ensured, the mixed test of multiple types of test boards is implemented, furthermore, the test efficiency is improved and the test cost is reduced.

The present application provides two-port on-wafer calibration piece circuit models and a method for determining parameters. The method includes: measuring a single-port on-wafer calibration piece circuit model corresponding to a first frequency band to obtain a first S parameter; calculating, according to the first S parameter, an intrinsic capacitance value of a two-port on-wafer calibration piece circuit model corresponding to the single-port on-wafer calibration piece circuit model; measuring the two-port on-wafer calibration piece circuit model corresponding to the terahertz frequency band to obtain a second S parameter; and calculating a parasitic capacitance value and a parasitic resistance value of the two-port on-wafer calibration piece circuit model according to the second S parameter and the intrinsic capacitance value.

A method of absolute phase calibration of at least a first port of a test and measurement equipment, comprising: providing the test and measurement equipment having the first port to be calibrated; providing a calibration mixer having a first port, a second port and a local oscillator port; providing at least one phase reproducible source that outputs a local oscillator signal; and performing at least two UOSM measurements at the first port of the test and measurement equipment, wherein at least one of the at least two UOSM measurements is performed with a frequency shift from a first frequency to a second frequency by using the calibration mixer. Furthermore, a calibration system is described.

A force-sense system can provide signals to, or receive signals from, a device under test (DUT) at a first DUT node. The system can include output buffer circuitry configured to provide a DUT signal to the DUT in response to a force control signal at a buffer control node, and controller circuitry configured to provide the force control signal at the buffer control node. The system can include bypass circuitry configured to selectively bypass the controller circuitry and provide an auxiliary control signal at the buffer control node. The auxiliary control signal can be used for system calibration. In an example, an external calibration circuit can provide the auxiliary control signal in response to information received from the DUT.

A method includes: constructing an on-wafer calibration piece model set that includes one or more on-wafer calibration piece models, where each of the one or more on-wafer calibration piece models has a corresponding on-wafer calibration piece; selecting an on-wafer calibration piece model from the on-wafer calibration piece model set; measuring the on-wafer calibration piece utilizing an on-wafer S parameter measurement system that is calibrated using a multi-thread TRL calibration method in a Terahertz frequency band, to obtain an S parameter of the on-wafer calibration piece; and calculating a plurality of different parameters that represent crosstalk of calibration pieces in the on-wafer calibration piece model, according to an admittance calculated according to the S parameter and an admittance formula corresponding to the on-wafer calibration piece model.

Embodiments of the present invention provide systems and methods for automatically performing TDR calibration to compensate for the time delay of a signal carried over a transmission environment (e.g., cable or other electrical path) used during DUT testing. A signal provider generates a signal along a signal path, and a circuit comprising a capacitor coupled to the signal provider and a diode coupled to the capacitor receives the signal periodically. A measurement unit coupled to the capacitor and the diode measures a voltage at the capacitor to determine a signal characteristic value of the signal along the signal path. The signal characteristic value is used to determine the electrical length (delay) of the transmission environment. TDR calibration is performed using the electrical length to compensate for the time delay/reflections over the transmission environment during testing. Advantageously, embodiments do not use a comparator circuit or a receiver circuit, and therefore can perform TDR calibration without significantly reducing the bandwidth of the testing equipment.

An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

A system and method for measuring or calibrating a delay through a circuit path within an integrated circuit is disclosed. In some embodiments, a delay locked loop (DLL) circuit is provided. An arbiter circuit in the DLL compares timing of a clock signal and a delayed version of the clock signal that has passed through the circuit path. The percentage of the clock signal with feature that arrives before the corresponding feature of the delayed clock can be an indication of the delay timing through the path relative to a period of the clock signal and used as feedback in the DLL.

A test system includes: an input signal generation unit that generates an input signal that drives a semiconductor device as a test target; a reference signal generation unit that supplies a reference signal, which is for use in generating the input signal, to the input signal generation unit; and a detection unit that, while implementing a test of the semiconductor device, generates a standard signal in which the same signal output as an output of the reference signal output from the reference signal generation unit is expected, and outputs a detection unit output signal based on the reference signal and the standard signal.

The invention concerns devices and methods for calibrating an Automated Test Equipment for automated testing of a Device Under Test. The method includes providing two digital channel signals by two different channels of the Automated Test Equipment, wherein the digital channel signals include an identical or a complementary pattern with respect to their edges. The method further includes sum-combining or difference-combining the two digital channel signals in order to obtain a combined residual signal. The step of combining is performed such that combining provides a combined residual signal without a time-variant component if the two digital channel signals have a predetermined time shift or a predetermined phase shift relative to each other, or such that the combined residual signal includes a time variant component if the two digital channel signals have a time shift different from the predetermined time shift or a phase shift different from the predetermined phase shift.