The present invention relates to a method for calibrating a channel delay skew of automatic test equipment (ATE), the method comprising: providing multiple calibration reference devices, wherein the calibration reference devices have a second plurality of delay paths each having a predetermined path delay value and coupling a pair of pins of one of the calibration reference devices together, wherein each pin is coupled to at most one delay path; coupling each of the calibration reference devices with the ATE, respectively, wherein the test probe of each of the first plurality of test channels is coupled with a pin of one of the calibration reference devices; testing the calibration reference devices to obtain multiple delay measurements from one or more transmitting channels of the first plurality of test channels to one or more receiving channels of the first plurality of test channels using the ATE; and calculating based on the delay measurements.

A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.

A device may determine an analog gain for an aggregated analog signal. The aggregated analog signal may be associated with a calibration test to be used to determine a set of calibration parameters for a load test of a base station. The device may determine the set of calibration parameters for the load test based on an outcome of performing a calibration test. The set of calibration parameters may result in a set of digital gains approximately centered in a digital dynamic gain range. The device may perform the load test after determining the analog gain for the analog signal and based on the set of calibration parameters for the load test.

In one embodiment, a tester calibration device includes a first board to be installed on one of a plurality of sockets of a tester for testing a semiconductor device, when the tester is to be calibrated. The device further includes a plurality of first pins provided on a first face of the first board, and to be made contact with the one socket when the tester is to be calibrated. The device further includes a wiring configured to electrically connect some of the plurality of first pins with each other.

A method includes setting a setting duty ratio of a pulse to a predefined first setting duty ratio, detecting a measured value of power of a microwave, and calculating an error of the measured value of the power with respect to the setting power level for each setting power level, calculating a correction value for the power for each setting power level on the basis of the error, and determining a first function indicating a relationship between the setting power level and the correction value by logarithmically approximating the relationship between the setting power level and the correction value, and determining the correction function indicating a relationship among the setting duty ratio, the setting power level, and the correction value by approximating the correction value defined by the first function, and the predefined correction value at a setting duty ratio of 100%, with a linear function.

An electromagnetic wave impedance measuring apparatus includes a network analyzer, configured to measure scattering parameters according to a frequency, including a first port and a second port; and a multilayer substrate, connected to the first port and the second port by a coaxial cable, having a via connecting conductive layers to each other and including three or more conductive layers including at least an uppermost layer, a lowermost layer, and an intermediate layer. The multilayer substrate includes a test sample disposed between the uppermost layer and the lowermost layer; a through calibration standard disposed between the uppermost layer and the lowermost layer; a reflect calibration standard disposed between the uppermost layer and the lowermost layer; and a line calibration standard disposed between the uppermost layer and the lowermost layer. Each of the test sample, the through calibration standard, the reflect calibration standard, and the line calibration standard is connected by a first error box, having the via, and a second error box having the via of the same structure as the via of the first error box.

A system and method for measuring or calibrating a delay through a circuit path within an integrated circuit is disclosed. In some embodiments, a delay locked loop (DLL) circuit is provided. An arbiter circuit in the DLL compares timing of a clock signal and a delayed version of the clock signal that has passed through the circuit path. The percentage of the clock signal with feature that arrives before the corresponding feature of the delayed clock can be an indication of the delay timing through the path relative to a period of the clock signal and used as feedback in the DLL.

A test apparatus for testing a device under test is configured to receive a response signal from the device under test and to apply one or more correction functions to the received response signal to at least partially correct an imperfection of the DUT. The test apparatus is configured to thereby obtain a corrected response signal of the device under test and to evaluate the corrected response signal to judge the device under test.

An electronic overload current breaker supports arc-fault and ground-fault (AFGF) detection along with built-in shunt calibration (BISC). The breaker may include a current sensing shunt and a control circuit electrically coupled to the current sensing shunt. This control circuit is configured to calibrate the current sensing shunt in response to application of a calibration current to the breaker. The control circuit can: (i) determine a magnitude of the calibration current applied to the breaker, (ii) map the magnitude of the calibration current to a first one of a plurality of current ratings for the breaker, and (iii) set the breaker to monitor overload conditions at the first one of the plurality of current ratings. The plurality of current ratings for the breaker can be less than the magnitude of the calibration current.

A test equipment has a signal input/signal output and a use-site calibration unit for determining a user-site compensation function. The user-site compensation function has a compensation magnitude function and a compensation Hilbert phase function. The calibration unit has a level meter and a calculator. The level meter is configured to measure a magnitude characteristic of the electrical signal, the magnitude characteristic being the basis for the determination of the compensation Hilbert phase function. The calculator is configured to determine a Hilbert phase characteristic of the electrical signal based on a Hilbert transformation of a function dependent on the measured magnitude characteristic and to determine the compensation Hilbert phase function on the basis of the Hilbert phase characteristic.