A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.

The present invention relates to a method for calibrating a channel delay skew of automatic test equipment (ATE), the method comprising: providing multiple calibration reference devices, wherein the calibration reference devices have a second plurality of delay paths each having a predetermined path delay value and coupling a pair of pins of one of the calibration reference devices together, wherein each pin is coupled to at most one delay path; coupling each of the calibration reference devices with the ATE, respectively, wherein the test probe of each of the first plurality of test channels is coupled with a pin of one of the calibration reference devices; testing the calibration reference devices to obtain multiple delay measurements from one or more transmitting channels of the first plurality of test channels to one or more receiving channels of the first plurality of test channels using the ATE; and calculating based on the delay measurements.

A network analyzer includes a main unit and a physically separate remote unit. In at least one configuration, the main unit generates and transmits test signals through a device under test to the remote unit. Reference circuitry in the main unit uses signals from a local oscillator and an analog-to-digital ADC sample clock to produce reference signal data representative of the test signals as transmitted to the device under test. Receive circuitry in the remote unit produces received signal data representative of the test signals as received from the device under test, using the same signals from the local oscillator and ADC sample clock as used by the reference circuitry to produce the reference signal data. Comparison of the received signal data with the reference signal data indicates parameters of the device under test, including attenuation and phase shift in the test signals as caused by the device under test.

Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.

A calibration arrangement for calibrating a power source includes first and second resistors with first and second resistances, respectively, which are usable in calibrating the power source. The second resistance is smaller than the first resistance and the calibration arrangement is configured to allow for a measurement of the first resistance of the first resistor. The calibration arrangement is configured to form a series connection of the first resistor and of the second resistor, to allow for at least two voltage measurements between at least two different pairs of circuit nodes of the series connection, wherein a same current is applied during the at least two voltage measurements, and to derive the second resistor with a second resistance on the basis of the at least two voltage measurements and a result of the measurement of the first resistance of the first resistor.

Provided are a test board and a test system for efficiently testing a semiconductor package, and a manufacturing method for the semiconductor package using the same. A test apparatus includes a field programmable gate array (FPGA) configured to output a first data signal to be transmitted to the semiconductor device and a second data signal to be transmitted to the semiconductor device and a memory configured to store a test result. The FPGA includes a first input/output block configured to output the first data signal, a second input/output block configured to output the second data signal, a serializer/deserializer (SerDes) circuit configured to generate a strobe signal, and a skew calibration input/output block configured to receive the first data signal from the first input/output block, the second data signal from the second input/output block, and the strobe signal from the SerDes circuit.

Systems and methods for calibrating a voltage measurement device are provided herein. The voltage measurement device generates a reference current signal and senses the reference current signal in a conductor under test. A calibration system may control a calibration voltage source to selectively output calibration voltages in a calibration conductor. The calibration system may obtain data from the voltage measurement device captured by the voltage measurement device when measuring the calibration conductor. Such data may include one or more reference current measurements, one or more voltage measurements, etc. The calibration system utilizes the obtained measurements to generate calibration data which may be stored on the voltage measurement device for use thereby during subsequent operation. The calibration data may include one or more lookup tables, coefficients for one or more mathematical formulas, etc.

A system that can include a computing device, upon implementing a host test program, can be configured to generate compiled host test instructions based on a non-host test program code that has been prepared in accordance with performance characteristics of a non-host automatic test equipment (ATE) and based on calibration data and/or offset data associated with a host ATE. The system can further include a hardware adapter that can be configured to generate non-host test signals based on host test signals generated by a host ATE and with substantially similar characteristics as test signals generated by the non-host ATE, wherein the host test signals are generated by the host ATE based on the compiled host test instructions.

A method includes: constructing an on-wafer calibration piece model set that includes one or more on-wafer calibration piece models, where each of the one or more on-wafer calibration piece models has a corresponding on-wafer calibration piece; selecting an on-wafer calibration piece model from the on-wafer calibration piece model set; measuring the on-wafer calibration piece utilizing an on-wafer S parameter measurement system that is calibrated using a multi-thread TRL calibration method in a Terahertz frequency band, to obtain an S parameter of the on-wafer calibration piece; and calculating a plurality of different parameters that represent crosstalk of calibration pieces in the on-wafer calibration piece model, according to an admittance calculated according to the S parameter and an admittance formula corresponding to the on-wafer calibration piece model.

A module for initializing and calibrating a product during the manufacture of the product in a manufacturing environment, wherein the module is able to be arranged on the product and wherein the module has a first interface for wireless data transmission between the module and the manufacturing environment, a second interface for establishing a data connection between the module and the product, an electrical energy source and a data processing unit. The module is designed to supply the product at least temporarily with energy by way of the energy source, to establish a data connection with the product via the second interface, to perform test and/or calibration routines on the product via the second interface, wherein the data processing unit generates test and/or calibration data during the performance of the test and/or calibration routines, and to transmit the test and/or calibration data to the manufacturing environment via the first interface.