A liquid crystal display device includes a first substrate spaced from a second substrate, a liquid crystal layer between the first and second substrates, a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate. The display device also includes a first switch and a second switch. The first switch is connected to the gate line, the data line, and the first sub-pixel electrode. The second switch is connected to the gate line, the data line, and the second sub-pixel electrode. The second switch includes a first gate electrode connected to the gate line and a second gate electrode not connected to the gate line.

A display device includes: a first substrate including a display area and a non-display area; a gate line in the display area and a gate pad in the non-display area, the gate line extending in a first direction; a data line in the display area, the data line extending in a second direction intersecting the first direction; a thin film transistor at an intersection point among the gate line and the data line; a step-difference pattern on the gate pad; and a protective layer including a first protective layer on the thin film transistor and a second protective layer on the step-difference pattern and the gate pad. The second protective layer has a height less than a height of the first protective layer.

An active element array substrate including a substrate, a first metal layer, a first insulation layer, a semiconductor layer, a first patterned conductive layer, a second metal layer, a second insulation layer, and a second patterned conductive layer is provided. The semiconductor layer is disposed on the first insulation layer. The first patterned conductive layer is disposed on the first insulation layer and covers a partial region of the semiconductor layer. The second metal layer is disposed on the first patterned conductive layer. The second insulation layer is disposed on the second metal layer and covers at least a partial region of the second metal layer, the first patterned conductive layer, the semiconductor layer, and the first insulation layer. The second patterned conductive layer is disposed on the second insulation layer and overlapped with the first patterned conductive layer. A display panel is also provided.

A flexible array substrate structure and manufacturing method thereof are disclosed, in which the patterning process of an organic semi-conductive layer is achieved by using the inside wall of the opening of a color film layer as a bank, so that one mask can be saved. Also, a process for manufacturing a device can be simplified by an improved device structure, so that the flexible array substrate structure of the invention can be obtained by only using four masks.

Disclosed are an LCD device and a method of manufacturing the same, in which a passivation layer and a pixel electrode are simultaneously formed by a single mask process using a half tone mask, and thus, manufacturing efficiency increases, and a defective contact due to loss of the pixel electrode can be prevented in a pad area. The LCD device includes a pad part including a pad area and a contact area. The LCD device includes a pixel pad formed in the pad area, a pixel bar formed in the contact area, and a bridge layer contacting the pixel pad with the pixel bar. The bridge layer is formed as a single layer or multi layers, and formed of one or more of a transparent conductive material and an opaque conductive material.

According to an embodiment of the present disclosure, a method for manufacturing the array substrate includes forming a first transparent conductive layer and a metallic layer successively on a base substrate, and forming a gate electrode, a source electrode, a drain electrode and a first transparent electrode by one patterning process.

An array substrate and a manufacturing method thereof, a display panel and a display device are disclosed. The method for manufacturing an array substrate includes: forming a first via hole (11) for connecting a second transparent electrically conductive layer (39) and a gate line layer (39), a second via hole (12) for connecting a first transparent electrically conductive layer (30) and the second transparent electrically conductive layer (39), and a third via hole (13) for connecting the second transparent electrically conductive layer (39) and a source/drain electrode layer (34) on a base substrate (10) through patterning process; performing a filling process on the first via hole (11), the second via hole (12) and the third via hole (13) during a pattern of second transparent electrically conductive layer is being formed, such that each of the first via hole, the second via hole and the third via hole which are filled has a top surface which is in the same horizontal plane as portions of the second transparent electrically conductive layer (39) surrounding the respective via holes. The method can reduce the height difference between the top surface of the via hole and the transparent electrically conductive layer surrounding the via hole and to solve the problem of uneven diffusion of the PI orientation layer.

A display device includes a display element including a first electrode, a protective layer arranged on the first electrode, a second electrode arranged on the protective layer at a pixel area and contacting a thin film transistor. A sensing line is arranged on the protective layer and contacts the first electrode through a contact hole exposing the first electrode through the third protective layer. The sensing line comprises a first conductive layer arranged on the protective layer and contacting the second electrode through the contact hole, and a second conductive layer arranged on the first conductive layer.

The invention discloses array substrate, manufacturing method thereof, display panel and display device, array substrate comprises TFTs, common electrodes, common electrode lines, data lines and gate lines, each TFT comprises gate, active layer corresponding to the gate, protective layer corresponding to the gate line or gate, and ESL, the active layer and protective layer are provided in the same layer and separated from each other; the ESL is provided with source holes and drain hole corresponding to the active layer, protective hole corresponding to the protective layer but not overlapping with the data line, and connecting holes corresponding to the common electrode and common electrode line; and distance between each connecting hole and the protective hole closest thereto is smaller than that between the connecting hole and the source or drain hole closest thereto, and/or, diameter of said protective hole is smaller than those of the source and drain holes.

The embodiments of the present invention provide an array substrate and a method for manufacturing the same. The method includes: forming an ITO film on a substrate; performing an annealing treatment on the substrate; forming a gate metal film on the ITO film; and processing the ITO film and the gate metal film to obtain a common electrode pattern and a gate pattern. In the embodiments of the present invention, after film formation of ITO, an annealing process is performed. Water vapor residue in the ITO film can thus be released, thereby avoiding bumps on the interface between the ITO and other layers, and improving the yield of ADS products.