To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Provided is a vertical alignment liquid crystal display, comprising a plurality of data lines, a plurality of scan lines and a plurality of common electrode lines; the scan lines intersect the data lines and the common electrode lines to form a plurality of pixel regions arranged in an array; the sub pixel region comprises a first thin film transistor, a second thin film transistor and a sub pixel, and gates of the first thin film transistor and second thin film transistor are coupled to a same scan line, and drains of the first thin film transistor and second thin film transistor are respectively coupled to a data line and a common electrode line which are adjacent, and sources of the first thin film transistor and second thin film transistor are coupled to the sub pixel; the main pixel region comprises a third thin film transistor and a sub pixel.

The disclosure provides a display panel, a method for making the display panel, and a method for controlling the display panel. The display panel comprises: multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions; multiple pixel electrodes in the multiple pixel regions; multiple first thin film transistors in the multiple pixel regions, the gates of the multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; and a second thin film transistor between and connecting two adjacent pixel electrodes, wherein the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state when the display panel is under a power failure condition.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

A display device comprising: a display portion that is provided on a thin-film transistor (TFT) substrate and that comprises pixel capacitors and pixel transistors included in a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, a plurality of scan lines each coupled to some of the pixels arranged in the first direction, and a plurality of video signal lines each coupled to some of the pixels arranged in the second direction; and a driver that is provided on the TFT substrate and that is configured to supply video signals to the video signal lines and to control the pixel transistors to be on and off through the scan lines.

The disclosure provides a display panel, a method for making the display panel, and a method for controlling the display panel. The display panel comprises: multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions; multiple pixel electrodes in the multiple pixel regions; multiple first thin film transistors in the multiple pixel regions, the gates of the multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; and a second thin film transistor between and connecting two adjacent pixel electrodes, wherein the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state when the display panel is under a power failure condition.

An active matrix substrate according to an aspect of the disclosure includes a pixel portion including a plurality of gate lines and a plurality of source lines, and a plurality of pixel electrodes, and a split switch circuit configured to split a signal from a source driver to supply to the plurality of source lines, wherein the pixel portion includes a first TFT including a first oxide semiconductor layer, the split switch circuit includes a second TFT including a second oxide semiconductor layer and a third oxide semiconductor layer, and the third oxide semiconductor layer covers at least a portion of an upper face and a portion of an edge face of the second oxide semiconductor layer.

A display device includes: a substrate; a gate line disposed on the substrate and configured to transmit a gate signal; a reference voltage line disposed apart from the gate line and configured to transmit a reference voltage; an insulation layer disposed on the gate line and the reference voltage line; a pixel electrode layer including: a first sub-pixel electrode disposed on the insulation layer and located at a first side with reference to the gate line; and a second sub-pixel electrode disposed on the insulation layer and located at a second side opposite to the first side with reference to the gate line; and a conductive shield portion disposed on the gate line, wherein the gate line includes two parallel edges, an edge closer to the reference voltage line among the two parallel edges including a first edge, and wherein the conductive shield portion overlaps the first edge.

A method for manufacturing an active matrix substrate including a thin film transistor disposed for each pixel, and a first electrode and a first wiring line for touchscreen panel function includes: (A) a step of forming an oxide semiconductor layer, a gate insulating layer, and a gate electrode on a substrate; (B) a step of forming an insulating layer covering the gate electrode, the gate insulating layer, and the oxide semiconductor layer, and having a source-side aperture and a drain-side aperture through which portions of the oxide semiconductor layer are exposed; (C) a step of forming a source electrode within the source-side aperture and a drain electrode within the drain-side aperture; (D) a step of forming an interlayer insulating layer including an organic insulating layer and having a first contact hole through which a portion of the drain electrode is exposed; (E) a step of forming a first transparent electrically conductive film on the interlayer insulating layer and within the first contact hole; (F) a step of forming by using a metal film, on a portion of the first transparent electrically conductive film, an upper wiring portion to become an upper layer of the first wiring line; (G) a step of patterning the first transparent electrically conductive film to make a pixel electrode and form a lower wiring portion to become a lower layer of the first wiring line; (H) a step of forming a dielectric layer covering the pixel electrode and the first wiring line and having a second contact hole through which a portion of the first wiring line is exposed; and (I) a step of forming, on the dielectric layer and within the second contact hole, a common electrode which is electrically connected to the first wiring line within the second contact hole. When viewed from a normal direction of the substrate, a bottom face of the first contact hole at least partially overlaps a bottom face of the drain-side aperture, and a bottom face of the second contact hole at least partially overlaps a bottom face of the source-side aperture.

A shift register unit, drive method thereof, gate drive device and display device. The shift register unit includes: an input subcircuit; a reset subcircuit; an output subcircuit configured to provide a clock signal at a clock signal end to a current stage shift register unit output end in response to a voltage signal at the pull-up node and a control signal having a first voltage level, and to disable an output at the current stage output end in response to the control signal having a second voltage level; a pull down control subcircuit configured to provide a second voltage signal having a low voltage level to a pull-down node in response to the voltage signal at the pull-up node, and to provide the voltage signal having a high voltage level to the pull-down node in response to the voltage signal having a high voltage level; and a pull down subcircuit.