A pixel unit and a display substrate are provided. The pixel unit has at least two sub-pixels arranged along a first direction or a second direction within a liquid crystal display panel, and each of the sub-pixels comprises a first area, a second area, and a third area, wherein a source/drain of the third-area thin film transistor connects to a third-area common electrode, and the third-area common electrode connects to a second input.

A novel input/output device that is highly convenient or reliable, or a novel data processor and a novel semiconductor device are provided. The inventors have devised a structure in which a display portion and an input portion are included; the display portion includes a first display element, a first conductive film electrically connected to the first display element, a second conductive film including a region overlapping with the first conductive film, an insulating film including a region between the second conductive film and the first conductive film, a pixel circuit electrically connected to the second conductive film, and a second display element electrically connected to the pixel circuit; the insulating film includes an opening; and the second conductive film is electrically connected to the first conductive film through the opening. The input portion has a function of sensing an object that approaches a region overlapping with the display portion.

A display device includes: a plurality of pixel electrodes arranged in the display region of a first substrate; a color filter provided on a second substrate opposing the first substrate and overlapping the pixel electrode; a planarization insulating layer provided on the color filter; a common electrode provided on the planarization insulating layer and having an opening; a spacer arranged between the pixel electrode and the common electrode; and a light-shielding layer provided between the first substrate and the pixel electrode and overlapping the spacer.

A manufacture method of a low temperature poly-silicon array substrate is provided. A halftone mask is utilized to realize a patterning process applied to a polysilicon layer and an N type heavy doping process of a polysilicon section of an NMOS region. In comparison with prior art, one mask is saved, and thus, the production cost is reduced, and a low temperature poly-silicon array substrate manufactured with such a process possesses excellent electronic property.

Provided is a vertical alignment liquid crystal display, comprising a plurality of data lines, a plurality of scan lines and a plurality of common electrode lines; the scan lines intersect the data lines and the common electrode lines to form a plurality of pixel regions arranged in an array; the sub pixel region comprises a first thin film transistor, a second thin film transistor and a sub pixel, and gates of the first thin film transistor and second thin film transistor are coupled to a same scan line, and drains of the first thin film transistor and second thin film transistor are respectively coupled to a data line and a common electrode line which are adjacent, and sources of the first thin film transistor and second thin film transistor are coupled to the sub pixel; the main pixel region comprises a third thin film transistor and a sub pixel.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

According to an aspect, a display apparatus includes: a display panel including a plurality of pixels each including a pixel capacitor and a pixel transistor, a scanning line that is coupled to the respective pixels and is configured to receive a scan signal, and a video signal line that is coupled to the respective pixels and is configured to receive a video signal; and a driver configured to drive the display panel. The pixel transistor includes: at least one N-channel metal oxide semiconductor (NMOS) transistor coupled between the video signal line and the pixel capacitor; and a P-channel metal oxide semiconductor (PMOS) transistor coupled in parallel with the NMOS transistor.

According to one embodiment, a liquid crystal display device includes a first substrate including a semiconductor layer including a first extension portion and a second extension portion, a gate line, a first common electrode opposed to at least the second extension portion, a source line extending above the second extension portion, a pixel electrode including a main pixel electrode, a second common electrode including a second main common electrode opposed to the source line, and a first alignment film.

An array substrate and a manufacturing method thereof, a display device and a driving method thereof. The array substrate includes: a first thin film transistor, a second thin film transistor and a pixel electrode, the pixel electrode being electrically connected to the first thin film transistor and the second thin film transistor, one of the first thin film transistor and the second thin film transistor being an n-type thin film transistor, and another one being a p-type thin film transistor.

A thin film transistor, a controlling method thereof, an array substrate and a display device. The thin film transistor includes: a substrate; and a gate electrode, an active layer, a source and a drain on the substrate. The source comprises two source electrodes electrically connected with each other; the drain comprises two drain electrodes electrically connected with each other, and the two drain electrodes are between the two source electrodes; and the active layer comprises primary channels between adjacent source electrodes and drain electrodes and a secondary channel between the two drain electrodes.