A display device comprising: a display portion that is provided on a thin-film transistor (TFT) substrate and that comprises pixel capacitors and pixel transistors included in a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, a plurality of scan lines each coupled to some of the pixels arranged in the first direction, and a plurality of video signal lines each coupled to some of the pixels arranged in the second direction; and a driver that is provided on the TFT substrate and that is configured to supply video signals to the video signal lines and to control the pixel transistors to be on and off through the scan lines.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

A substrate includes a base material having an insulating property, a pixel electrode provided on one surface side of the base material, a pixel transistor provided between the base material and the pixel electrode, a first reflective film provided between the pixel transistor and the pixel electrode, and a common electrode provided between the pixel transistor and the first reflective film. The first reflective film has a first through-hole, the common electrode has a second through-hole, and a drain of the pixel transistor is coupled to the pixel electrode through the first through-hole and the second through-hole.

A liquid crystal display is provided, including a first thin film transistor layer and a first color filter arranged on an array substrate, and a color filter substrate arranged opposite the array substrate, where a second thin film transistor layer and a second color filter are disposed on the color filter substrate, a color resist of the first color filter is staggered with a color resist of the second color filter. Advantages of the disclosure include increase transmittance and reduced energy consumption.

A liquid crystal display is provided, including a first thin film transistor layer and a first color filter arranged on an array substrate, and a color filter substrate arranged opposite the array substrate, where a second thin film transistor layer and a second color filter are disposed on the color filter substrate, a color resist of the first color filter is staggered with a color resist of the second color filter. Advantages of the disclosure include increase transmittance and reduced energy consumption.

A manufacture method of a low temperature poly-silicon array substrate is provided. A halftone mask is utilized to realize a patterning process applied to a polysilicon layer and an N type heavy doping process of a polysilicon section of an NMOS region. In comparison with prior art, one mask is saved, and thus, the production cost is reduced, and a low temperature poly-silicon array substrate manufactured with such a process possesses excellent electronic property.

The present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Disclosed are a pixel structure and a liquid crystal display device. A data line and a common line are arranged in a same layer and are parallel to each other. A pixel area is located in a region surrounded by a scanning line and the data line. The pixel area includes a sub area which includes a first thin film transistor. Since the data line and the common line are arranged in a same layer, a through hole is no longer needed in connection of a source of the first thin film transistor and the common line. Hence, one through hole is omitted, thereby improving an aperture ratio of a pixel.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.