To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

A display panel and an electronic device with a narrow lower border. The display panel includes a left border, a right border and a lower border. The lower border has a length direction extending from the left border to the right border. The lower border is provided with a first detection area, a first installation area, a bonding area, a second installation area and a second detection area which are arranged sequentially along the length direction. The bonding area is used to bond a flexible circuit board. The first installation area is used to install a first driving chip. The second installation area is used to install a second driving chip. The first detection area and the second detection area are used to transmit test signals to the display panel before bonding the flexible circuit board and before installing the first driving chip and the second driving chip.

An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.

In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.

In various embodiments, electronic devices such as thin-film transistors and/or touch-panel displays incorporate bilayer capping layers and/or barrier layers.

The application provides a display substrate and a display device. The display substrate includes: gate lines, data lines, the gate lines and the data lines being arranged to intersect to define sub-pixels, every multiple sub-pixels in a same row constituting a pixel unit; and common electrode lines, each of the common electrode lines is between adjacent two of the gate lines. The display substrate further includes common voltage input line groups intersecting with the common electrode lines. Common voltage input lines in different groups are electrically connected to different ones of the common electrode lines, respectively; and an orthographic projection of every N columns of pixel units on a substrate covers an orthographic projection of a corresponding one of the common voltage input line groups on the substrate, where N is an integer greater than or equal to 1.

According to one embodiment, a semiconductor substrate including, a switching element, a first organic insulating film, first and second metal lines arranged in a first direction and extending in a second direction, and a metal electrode located between the first and second metal lines. The first organic insulating film includes first and second surfaces. The switching element is covered with the first surface. The first and second metal lines and the metal electrode are located on the second surface side. The first metal line includes a first portion extending in the second direction and a second portion having a width larger than a width of the first portion. The second portion includes arcuate first and second edge. The metal electrode has a polygonal shape having n corners or an elliptic shape where n is larger than four.

A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.

A liquid crystal display device includes a transistor, a pixel electrode, and a common electrode. The transistor includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a first oxide conductive layer and a second oxide conductive layer disposed between the first insulating layer and the oxide semiconductor layer and disposed with the first gate electrode and the second gate electrode sandwiched from both sides. The pixel electrode is disposed between the first and the second insulating layer; the common electrode is disposed a region overlapping with the pixel electrode and on the second insulating layer.

It is possible to reduce a size of a lower frame region to ensure a wiring corrosion margin equivalent to that of a conventional technique. In a display device, a video signal wiring arranged in the lower frame region includes, in a region between a terminal section (terminal) and a video signal line, a first wiring formed on a first wiring layer and having one end connected to the terminal section to which a video signal line driving circuit is connected, a second wiring formed on a second wiring layer different from the first wiring layer and having one end connected to the other end of the first wiring, and a third wiring formed on the first wiring layer and having one end connected to the other end of the second wiring. The other end of the third wiring is connected to the video signal line via a fourth wiring formed on the second wiring layer, and the first wiring layer is formed on the side closer to an array substrate than to the second wiring layer.